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www.gennum.com gs1582 multi-rate serializer with cable driver, audio multiplexer and clockcleaner ? gs1582 data sheet 40117 - 1 november 2007 1 of 114 key features ? hd-sdi, sd-sdi, dvb-asi transmitter with audio embedding ? integrated smpte 292m and 259m-c compliant cable driver ? integrated clockcleaner ? ? user selectable video processing features, including: ? generic ancillary data insertion ? support for hvf or eia/cea-861 timing input ? automatic standard detection and indication ? enhanced smpte 352m payload identifier generation and insertion ? trs, crc, anc data checksum, and line number calculation and insertion ? edh packet generation and insertion ? illegal code remapping ? smpte 292m and smpte 259m-c compliant scrambling and nrz nrzi encoding ? blanking of input hanc and vanc space ? user selectable audio processing features, including: ? smpte 299m and smpte 272m-a/c compliant audio embedding ? support for up to 8 channels ? support for audio group replacement ? jtag test interface ? 1.8v core and 3.3v charge pump power supply ? 1.8v and 3.3v digital i/o support ? low power standby mode ? operating temperature range: -20 o c to +85 o c ? pb-free, rohs compliant, 11mm x 11mm 100-ball bga package applications ? smpte 292m and smpte 259m-c serial digital interfaces ? dvb-asi serial digital interfaces description the gs1582 is the next generation multi-standard serializer with an integrated cable driver. the device provides robust parallel to serial conversion, generating a smpte 292m/259m-c compliant serial digital output signal. the integrated cable driver features an output disable (high impedance) mode and an adjustable signal swing. data input is accepted in 20-bit parallel format or 10-bit parallel fo rmat. an associated parallel clock input must be provided at the appropriate operating frequency; 74. 25/74.1758/13.5mhz (20-bit mode) or 148.5/148.352/27mhz (10-bit mode). the gs1582 features an internal pll which, if desired, can be configured for a loop bandwidth below 100khz. when used in conjunction with the go1555 voltage controlled oscillator, the gs 1582 can tolerate well in excess of 300ps jitter on the input pclk and still provide output jitter withi n smpte specifications. in addition to serializing the input, the gs1582 performs nrz-to-nrzi encoding and scrambling as per smpte 292m/259m-c when operating in smpte mode. when operating in dvb-asi mode, the device will insert k28.5 sync characters and 8b/10b encode the data prior to serialization. the device also provides a range of other data processing functions. all processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. the gs1582 can embed up to 8 channels of audio into the video data stream in accordance with smpte 299m and smpte 272m. the audio input signal formats supported by the device in clude aes/ebu and i 2 s serial digital formats with a 16, 20 or 24 bit sample size and a 48 khz sample rate. additional audio processing features include individual channel enable, channel swap, group swap, ecc generation and audio channel status insertion. typical power consumption, including the go1555 vco, is 500mw. the standb y feature allows the power to be reduced to 125mw. power may be reduced to less than 10mw by also removing the power to the cable driver and eliminating transi tions at the parallel data and clock inputs. the gs1582 is pb-free and rohs compliant.
gs1582 data sheet 40117 - 1 november 2007 2 of 114 functional block diagram gs1582 functional block diagram input mux/ demux din[19:0] sd/hd audio embedding smpte 352m generation and insertion anc data insertion trs, line number and crc insertion edh packet insertion nrz/nrzi smpte scrambler dvb asi endec f/de v/vsync h/hsync tim_861 parallel to serial converter mux smpte cable driver sdo sdo rset sdo_en/dis pclk aclk1 aclk2 wclk1 wclk2 ain_1/2 ain_3/4 ain_5/6 ain_7/8 audio_int grp1_en/dis grp2_en/dis gspi host interface hanc/ vanc blanking phasedetector/ chargepump cp_res lf vco 2.5v regulator vco_vcc vco_gnd locked cs_t ms sclk_tclk sdin_tdi sdout_tdo dvb_asi clockcleaner?
gs1582 data sheet 40117 - 1 november 2007 3 of 114 contents key features.................................................................................................................1 applications................................................................................................................... 1 description .................................................................................................................... 1 functional block diagram .............................................................................................2 1. pin out ..................................................................................................................... .7 1.1 pin assignment ...............................................................................................7 1.2 pin descriptions ..............................................................................................8 2. electrical characteristics .........................................................................................17 2.1 absolute maximum ratings ..........................................................................17 2.2 recommended operating conditions ........ .............. .............. .............. .........17 2.3 dc electrical characteristics ............. ...........................................................18 2.4 ac electrical characteristics .............. ...........................................................19 2.5 solder reflow profiles ...................................................................................21 3. input/output circuits ...............................................................................................22 4. detailed description .................................. ..............................................................25 4.1 functional overview .....................................................................................25 4.2 parallel data inputs ............................ ...........................................................26 4.2.1 parallel input in smpte mode.............................................................26 4.2.2 parallel input in dvb-asi mode...........................................................26 4.2.3 parallel input in data-through mo de...................................................27 4.2.4 parallel input clock (pclk) .................................................................27 4.3 smpte mode ................................................................................................28 4.3.1 hvf timing..........................................................................................28 4.3.2 cea 861 timing...................................................................................29 4.4 dvb-asi mode ....... .............. .............. .............. .............. ........... ........... .........34 4.4.1 control signal inputs ...........................................................................34 4.5 data-through mode ......................................................................................35 4.6 standby mode ..... .............. .............. .............. .............. .............. ........... .........35 4.7 audio multiplexer ..........................................................................................36 4.7.1 audio core configurat ions...................................................................36 4.7.2 audio detection ...................................................................................37 4.7.3 audio modes of operation ...................................................................38 4.7.4 audio packet delete ............................................................................39 4.7.5 arbitrary, smpte 352m & edh pack et detect .... ........... ........... .........40 4.7.6 audio packet multiplexing.............. ......................................................41 4.7.7 audio insertion after video switch ing point ........................................41 4.7.8 audio data packets .............................................................................42 4.7.9 audio control packets .........................................................................45 4.7.10 setting packet did ............................................................................47 4.7.11 audio group replacement ................................................................48
gs1582 data sheet 40117 - 1 november 2007 4 of 114 4.7.12 channel and group activation...........................................................50 4.7.13 ecc error detection & correction (hd mode only) ..........................50 4.7.14 interrupt control.................................................................................50 4.7.15 audio clocks......................................................................................50 4.7.16 5-frame sequence detection .......... .............. .............. .............. .........51 4.7.17 audio input format ............................................................................52 4.7.18 audio channel status input ...............................................................55 4.7.19 audio crosspoint ...............................................................................56 4.7.20 audio word clock ..............................................................................57 4.7.21 gs1582 sd audio fifo block ..........................................................58 4.7.22 audio sample distributions................................................................59 4.7.23 audio mute.........................................................................................62 4.8 ancillary data insertion .................................................................................62 4.8.1 ancillary data insertion operati ng mode .............................................63 4.8.2 hanc insertion....................................................................................64 4.8.3 vanc insertion ....................................................................................65 4.9 additional processing functions ...................................................................65 4.9.1 anc data blanking..............................................................................65 4.9.2 automatic video standard detection .............. .............. .............. .........65 4.9.3 video standard indication....................................................................66 4.9.4 packet generation and insertion .........................................................68 4.10 parallel to serial conv ersion .......................................................................73 4.11 internal clockcleaner tm pll ......................................................................74 4.11.1 external vco .....................................................................................74 4.11.2 loop filter..........................................................................................74 4.11.3 lock detect output ............................................................................75 4.12 serial digital output ......................... ...........................................................76 4.12.1 output swing .....................................................................................76 4.13 gspi host interface ....................................................................................76 4.13.1 command word description........... ...................................................78 4.13.2 data read and write timing ....... ......................................................78 4.13.3 configuration and status registers ...................................................80 4.14 jtag test operation ................................................................................105 4.15 device reset .............................................................................................107 5. application reference design ...............................................................................108 5.1 typical application circuit (part a) .............................................................108 5.2 typical application circuit (part b) .............................................................109 6. references & relevant standards ........................................................................110 7. package & ordering information ...........................................................................111 7.1 package dimensions ..................................................................................111 7.2 marking diagram .........................................................................................112 7.3 packaging data ...........................................................................................112 7.4 ordering information ...................................................................................112 8. revision history ....................................................................................................113
gs1582 data sheet 40117 - 1 november 2007 5 of 114 list of figures figure 2-1: maximum pb-free so lder reflow profile ..................................................21 figure 3-1: differential output stage (sdo/sdo ) .....................................................22 figure 3-2: charge pump current setting re sistor (cp_res) ..................................22 figure 3-3: pll loop filter ........................................................................................23 figure 3-4: vco input ................................................................................................23 figure 3-5: digital input pin with weak pull up(>33kw) (aclk[2:1], wclk[2:1], ain[4:1], pclk, din[19:0]) .................................................24 figure 3-6: 5v tolerant input pin (all other input pins) ..... .............. .............. ............24 figure 3-7: digital output pin with high impedance mode (locked, audio_int, sdout_tdo) ............ .........................................................24 figure 4-1: pclk to data timing ...............................................................................26 figure 4-2: h_blanking, v_blanking, f_digital timing ..............................................29 figure 4-3: hsync:vsync:de input timing 1280 x 720p @ 59.94/6 0 ........... .........31 figure 4-4: hsync:vsync:de input timing 19 20 x 1080i @ 59.94/60 .......... .........31 figure 4-5: hsync:vsync:de input timing 720 (1440) x 480i @ 59.94/60 ...........32 figure 4-6: hsync:vsync:de input timing 1280 x 720p @ 50 ....... .............. .........33 figure 4-7: hsync:vsync:de input timing 19 20 x 1080i @ 50 ...... .............. .........33 figure 4-8: hsync:vsync:de input timing 720 (1440) x 576 @ 50 ............. .........34 figure 4-9: dvb-asi fifo im plementation using the gs1582 .............. ........... .........35 figure 4-10: audio multiplexer top level ....... ...........................................................37 figure 4-11: ancillary data packet placement example ............................................39 figure 4-12: sd audio data packet structure ...........................................................42 figure 4-13: sd extended audio data packet structure ...... .............. .............. .........43 figure 4-14: hd audio data packet structure .. .........................................................43 figure 4-15: sd audio control packet structur e .......................................................45 figure 4-16: hd audio control packet structure .......................................................46 figure 4-17: audio group replacement example (hd formats) ...............................49 figure 4-18: aclk to data & control signal in put timing .........................................51 figure 4-19: aes/ebu sub-frame formatting .. .............. ............ ........... ........... .........54 figure 4-20: aes/ebu audio input format ....... .............. ............ ........... ........... .........54 figure 4-21: serial audio input: left justifie d; msb first ..........................................54 figure 4-22: serial audio input: left justifie d; lsb first ...........................................55 figure 4-23: serial audio input: right justif ied; msb first ........................................55 figure 4-24: serial audio input: right justifi ed; lsb first .........................................55 figure 4-25: i 2 s audio input .......................................................................................55 figure 4-26: gennum serial peripheral interf ace (gspi) ..... .............. .............. .........77 figure 4-27: command word .....................................................................................78 figure 4-28: data word ..............................................................................................78 figure 4-29: gspi read mode timing ............ ...........................................................79 figure 4-30: gspi write mode timing ............ .............. .............. ........... ........... .........79 figure 4-31: in-circuit jtag ....................................................................................106 figure 4-32: system jtag .......................................................................................106 figure 4-33: reset pulse .........................................................................................107
gs1582 data sheet 40117 - 1 november 2007 6 of 114 list of tables table 1-1: pin descriptions .......................................................................................... 8 table 2-1: recommended operating conditions ....................................................... 17 table 2-2: dc electrical characteristics .......... .......................................................... 18 table 2-3: ac electrical characteristics........ ............................................................. 19 table 4-1: parallel data input format ........... .............. .............. .............. .............. ..... 27 table 4-2: standby power consumption ................................................................... 36 table 4-3: audio multiplexer modes of operat ion ...................................................... 39 table 4-4: non-audio ancillary data packet di ds .............. ........... ............ ........... ..... 40 table 4-5: audio data packet word description s ...................................................... 42 table 4-6: extended audio data packet word descriptions...................................... 43 table 4-7: audio data packet word description s ...................................................... 44 table 4-8: audio control packet word descript ions .................................................. 45 table 4-9: audio control packet word descript ions .................................................. 46 table 4-10: audio group did host interface se ttings ............................................... 48 table 4-11: audio data and control packet di d setting register ............................. 48 table 4-12: gs1582 serial audio data inputs ... ........................................................ 51 table 4-13: frame rates with afn = 0...................................................................... 52 table 4-14: frame rates with varying samples per frame ........................................ 52 table 4-15: audio input formats.. .............. .............. .............. .............. .............. ........ 53 table 4-16: audio channel status block defaul t settings ........ .............. .............. ..... 56 table 4-17: audio channel status information register settings ..... ............ ............. 56 table 4-18: audio channel mapping codes ...... .............. .............. ............ ........... ..... 57 table 4-19: source input address registers ... .......................................................... 57 table 4-20: audio clock selection host interf ace settings........................................ 58 table 4-21: audio buffer pointe r offset settings ....................................................... 59 table 4-22: 5-frame sequence sample distribut ion .................................................. 59 table 4-23: group 1 audio sample distribution. .............. .............. ............ ........... ..... 60 table 4-24: group 2 audio sample distribution. .............. .............. ............ ........... ..... 60 table 4-25: group 3 audio sample distribution. .............. .............. ............ ........... ..... 60 table 4-26: group 4 audio sample distribution. .............. .............. ............ ........... ..... 60 table 4-27: group 1 audio sample distribution. .............. .............. ............ ........... ..... 61 table 4-28: group 2 audio sample distribution. .............. .............. ............ ........... ..... 61 table 4-29: group 3 audio sample distribution. .............. .............. ............ ........... ..... 61 table 4-30: group 4 audio sample distribution. .............. .............. ............ ........... ..... 61 table 4-31: synchronous audio sample distri butions ............................................... 62 table 4-32: host interface description for vi deo standard register ......................... 66 table 4-33: host interface description for ra ster structure registers ..................... 66 table 4-34: supported video standards ............ .............. .............. ............ ........... ..... 67 table 4-35: host interface description for inte rnal processing disable register ...... 69 table 4-36: host interface description for smpte 352m packet line number insertion registers ........................................ ............................................................. 70 table 4-37: host interface description for smpte 352m payload identifier registers .................................................................................................................... 7 0 table 4-38: host interface description for ed h flag register (sd mode only)........ 72 table 4-39: serial digital outp ut rates...................................................................... 74 table 4-40: loop filter component values ............................................................... 75 table 4-41: gspi timing parame ters ........................................................................ 79 table 4-42: gs1582 internal regi sters...................................................................... 80 table 4-43: video configuration and status re gisters .............................................. 81 table 4-44: sd audio configuration and status registers ........................................ 88 table 4-45: hd audio configuration and status registers ........................................ 98
gs1582 data sheet 40117 - 1 november 2007 7 of 114 1. pin out 1.1 pin assignment 1 3 2 45 6 7 8 9 10 a b c d e f g h j k locked pclk din16 din15 din14 din12 din10 din8 din6 din4 din2 din1 din19 din13 din11 din9 din7 din5 din3 din0 sd/hd cp_vdd io_vdd anc_ io_vdd core _vdd io_gnd core _vdd core _gnd core _gnd detect _trs dvb_asi smpte_ bypass 20bit/ 10bit sdin _tdi sclk _tclk sdout _tdo cs_ tms cd_vdd rset tim 861 grp2_ en/dis nc lf sdo sdo vco_ vcc vco_ gnd din17 vco cd_gnd pd_vdd audio _int v/vsync io_gnd cd_gnd standby aclk_1 ain_1/2 nc nc jtag/ host sdo_en/ dis reset ioproc _en/dis wclk_2 wclk_1 nc nc ain_3/4 nc aclk_2 ain_5/6 ain_7/8 din18 f/de vco_ gnd cp_res pd_vdd core _gnd core _gnd core _gnd core _gnd h/hsync cp_gnd cd_gnd core _gnd core _gnd core _gnd core _gnd cd_gnd core _gnd core _vdd core _gnd core _vdd pd_gnd pd_gnd pd_gnd grp1_ en/dis rsv blank
gs1582 data sheet 40117 - 1 november 2007 8 of 114 1.2 pin descriptions table 1-1: pin descriptions pin number name timing type description a1, a2, b1, b2, b3, c1, c2, c3, d1, d2 din[19:10] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din19 is the msb and din10 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high luma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low multiplexed luma and chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low sd 20-bit mode sd/hd = high 20bit/10bit = high luma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low multiplexed luma and chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi mode smpte_bypass = low dvb_asi = high
gs1582 data sheet 40117 - 1 november 2007 9 of 114 a3 f/de synchronous with pclk input parallel data timing signal levels are lvcmos/lvttl compatible. tim_861 = low: used to indicate the odd / even field of the video signal when detect_trs is set low. the device wi ll set the f bit in all outgoing trs signals for the entire period that the f input signal is high (ioproc_en/dis must also be high). the f signal should be set high for the entire period of field 2 and should be set low for all lines in fiel d 1 and for all lines in progressive scan systems. the f signal is ignored when detect_trs = high. tim_861 = high: the de signal is used to indicate the active video period. de is high for active data and low for blanking. see section 4.3.1 and section 4.3.2 for timing details. the de signal is ignored when detect_trs = high. a4 h/hsync synchronous with pclk input parallel data timing signal levels are lvcmos/lvttl compatible. tim_861 = low: the h signal is used to indicate t he portion of the video line containing active video data, when detect_trs is set low. active line blanking the h signal should be set high fo r the entire horizontal blanking period, including the eav and sav trs words, and low otherwise. this is the default setting. trs based blanking (h_config = 1 h ) the h signal should be set high fo r the entire horizontal blanking period as indicated by the h bit in the received trs id words, and low otherwise. the h signal is ignored when detect_trs = high. tim_861 = high: the hsync signal indicates horizontal timing. see section 4.3.1 for timing details. the hsync signal is ignored when detect_trs = high. a5, e1, g10, k8 core_vdd non synchronous input power power supply connection for the digital core logic. connect to +1.8v dc digital. a6, b6 pd_vdd analog input power power supply connection for the phase detector. connect to +1.8v dc analog. a7 lf analog input pll loop filter connection. a8 vco_vcc analog output power power supply for the external voltage controlled oscillator. 2.5v dc supplied by the device to the external vco. a9 vco analog input input from external vco. a10 cp_vdd analog input power power supply connection for the charge pump and on chip vco regulator. connect to +3.3v dc analog. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 10 of 114 b4 pclk ? input parallel data bus clock signal levels are lvcmos/lvttl compatible. hd 20-bit mode pclk = 74.25mhz or 74.25/1.001mhz hd 10-bit mode pclk = 148.5mhz or 148.5/1.001mhz sd 20-bit mode pclk = 13.5mhz sd 10-bit mode pclk = 27mhz b5, c5, d5, e2, e5, e6, e7, f5, f6, f7, g9, j8 core_gnd non synchronous input power ground connection for the digital core logic. connect to digital gnd. c6, c7, c8 pd_gnd analog input power ground connection for the phase detec tor. connect to analog gnd. b7 cp_res ? input charge pump current setting resistor. b8, b9 vco_gnd analog output power ground pins for the vco. b10 cp_gnd analog input power ground pin for the charge pump and pll. c4 v/vsync synchronous with pclk input parallel data timing signal levels are lvcmos/lvttl compatible. tim_861 = low: the v signal is used to indicate the portion of the video field/frame that is used for vertical blanking, when detect_trs is set low. the v signal should be set high for the entire vertical blanking period and should be set low for all lines outside of the vertical blanking interval. the v signal is ignored when detect_trs = high. tim_861 = high: the vsync signal indicates vertical timing. see section 4.3.1 for timing details. the vsync signal is ignored when detect_trs = high. c9, d9, e9, f9 cd_gnd analog input power ground connection for the serial digital cable driver. connect to analog gnd. c10, d10 sdo, sdo analog output serial digital output signal operating at 1.485gb/s, 1.485/1.001gb/s, or 270mb/s. the slew rate of these outputs is automatically controlled to meet smpte 292m and 259m requirements according to the setting of the sd/hd pin. serial digital output signal from the internal cable driver. note: the sdo/sdo output signals will be set to high impedance when reset = low. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 11 of 114 d3 standby non synchronous input control signal input signal levels are lvcmos/lvttl compatible. power down input. when set high, the device will be in standby mode. d4 sdo_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable the serial digital output stage. when set low, the serial digi tal output signals sdo and sdo are disabled and become high impedance. when set high, the serial digital output signals sdo and sdo are enabled. the sdo and sdo outputs will also be high impedance when the reset pin is low. d6, d7, d8, e4, e8, f8 nc ? ? no connect. not connected internally. e3 sd/hd non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set low, the device will be configured to transmit signals of 1.485gb/s - 1.485/1.001gb/s rates only. when set high, the device will be configured to transmit signals of a 270mb/s rate only. e10 cd_vdd analog input power power supply connection for the serial digital cable driver. connect to +3.3v dc analog. f1, f2, h1, h2, j1, j2, j3, k1, k2, k3 din[9:0] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din9 is the msb and din0 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high chroma data input in smpte mode smpte_bypass =high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low high impedance in all modes. sd 20-bit mode sd/hd = high 20bit/10bit = high chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low forced low in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low high impedance in all modes. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 12 of 114 f3 detect_trs non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select external hvf ti ming mode or trs extraction timing mode. when detect_trs = low, the device will use timing from the externally supplied h:v:f or cea-861 timing signals, dependent on the state of the tim_861 pin. when detect_trs = high, the device will extract timing from trs signals embedded in the supplied video stream. f4 rsv ? ? reserved. do not connect. f10 rset analog input an external 1% resistor connected to this input is used to set the sdo/sdo output amplitude. g1, h10 io_vdd non synchronous input power power supply connection for digital i/o buffers. connect to +3.3v or +1.8v dc digital. g2, h9 io_gnd non synchronous input power ground connection for digital i/o buf fers. connect to digital gnd. g3 tim_861 non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select external cea-861 timing mode. when detect_trs = low and tim_861 = low, the device will use externally supplied h:v:f timing signals. when detect_trs = low and tim_861 = high, the device will use externally supplied hsync, vsync, de timing signals. when detect_trs = high, the device will extract timing from trs signals embedded in the supplied video stream. g4 20bit/10bit non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select the input data bus width. g5 dvb_asi non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set high, the device is configured for the transmission of dvb-asi data in sd mode (sd/hd = high). when set low, the device will not support the encoding of dvb-asi data. note: when operating in dvb-asi mode the sd/hd pin must be set high and smpte_bypass must be set low. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 13 of 114 g6 smpte_bypass non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable/disable all forms of encoding/decoding, scrambling and edh insertion. when set low, the device will operate in data through mode (dvb_asi = low), or in dvb-asi mode (dvb_asi = high). no smpte scrambling will take place and none of the i/o processing features of the device will be available when smpte_bypass is set low. when set high, the device will perform smpte scrambling and i/o processing. g7 ioproc_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable i/o processing features. when set high, the following i/o proc essing features of the device are enabled: ? audio embedding ? edh packet generation and insertion (sd-only) ? smpte 352m packet generation and insertion ? anc data checksum calculation ? anc data insertion ? line-based crc generation and insertion (hd-only) ? line number generation and insertion (hd-only) ? trs generation and insertion ? illegal code remapping to enable a subset of these features, set ioproc_en/dis = high and disable the individual feature(s) in the ioproc_disable register accessible via the host interface. when set low, the i/o processing feat ures of the device are disabled, and can not be enabled by changing the settings in the ioproc_disable register. g8 reset non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to reset the internal operating conditions to default settings and to reset the jtag test sequence. normal mode (jtag/host = low) when set low, all functional blocks will be set to default conditions and all input and output signals become high impedance including the serial digital outputs sdo and sdo. when set high, normal operation of the device resumes 10usec after the low to high transition of the reset signal. jtag test mode (jtag/host = high) when set low, all functional blocks will be set to default and the jtag test sequence will be held in reset. when set high, normal operation of the jtag test sequence resumes. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 14 of 114 h3 anc_blank non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable anc data blanking. when set low, the hanc and vanc data is mapped to the appropriate blanking levels. h4 locked synchronous with pclk output status signal output signal levels are lvcmos / lvttl compatible. this signal is set high by the device when the internal pll has achieved lock to the supplied pclk signal. this pin is set low by the de vice under all other conditions. io_vdd = 3.3v drive strength = 8ma io_vdd = 1.8v drive strength = 4ma h5 grp2_en/dis non synchronous input enable input for audio group 2. h6 grp1_en/dis non synchronous input enable input for audio group 1. h7 audio_int non synchronous output status signal output signal levels are lvcmos/lvttl compatible. summary interrupt from audio processing. this signal is set high by the devic e to indicate a problem with the audio processing which requires the host processor to interrogate the interrupt status registers. io_vdd = 3.3v drive strength = 8ma io_vdd = 1.8v drive strength = 4ma h8 jtag/host non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured for jtag boundary scan testing. when set low, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured as gennum serial peri pheral interface (gspi) pins for normal host interface operation. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 15 of 114 j4 ain_5/6 synchronous with aclk_2 input serial audio input; channels 5 and 6. j5 wclk_2 clock input 48khz word clock for audio group 2. j6 ain_1/2 synchronous with aclk_1 input serial audio input; channels 1 and 2. j7 wclk_1 clock input 48khz word clock for audio group 1. j9 sdout_tdo synchronous with sclk_tck output communication signal output signal levels are lvcmos/lvttl compatible. serial data output / test data output host mode (jtag/host = low) this pin operates as the host interfac e serial output, used to read status and configuration information from t he internal registers of the device. jtag test mode (jtag/host = high) this pin is used to shift test result s and operates as the jtag test data output, tdo. note: if the host interface is not being used leave this pin unconnected. io_vdd = 3.3v drive strength = 12ma io_vdd = 1.8v drive strength = 4ma j10 sclk_tck non synchronous input communication signal input signal levels are lvcmos/lvttl compatible. serial data clock / test clock. host mode (jtag/host = low) sclk_tck operates as the host interface burst clock, sclk. command and data read/write words are clocked into the device synchronously wi th this clock. jtag test mode (jtag/host = high) this pin is the test mode start pin, used to control the operation of the jtag test clock, tck. note: if the host interface is not being used, tie this pin high. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 16 of 114 k4 ain_7/8 synchronous with aclk_2 input serial audio input; channels 7 and 8. k5 aclk_2 clock input 3.072mhz audio clock for audio group 2 (channels 5-8). k6 ain_3/4 synchronous with aclk_1 input serial audio input; channels 3 and 4. k7 aclk_1 clock input 3.072mhz audio clock for audio group 1(channels 1-4). k9 cs_tms synchronous with sclk_tck input communication signal input signal levels are lvcmos/lvttl compatible. chip select / test mode start. host mode (jtag/host = low) cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag/host = high) cs _tms operates as the jtag test mode start, tms, used to control the operation of the jtag test, and is active high. note: if the host interface is not being used, tie this pin high. k10 sdin_tdi synchronous with sclk_tck input communication signal input signal levels are lvcmos/lvttl compatible. serial data in / test data input host mode (jtag/host = low) this pin operates as the host interfac e serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag/host = high) this pin is used to shift and operates as the jtag test data input, tdi. note: if the host interface is not being used, tie this pin high. table 1-1: pin descriptions (continued) pin number name timing type description
gs1582 data sheet 40117 - 1 november 2007 17 of 114 2. electrical characteristics 2.1 absolute maximum ratings 2.2 recommended operating conditions parameter value/units supply voltage, core (core_vdd) -0.3v to +2.1v supply voltage, analog 1.8v (pd_vdd) -0.3v to +2.1v supply voltage, i/o (io_vdd) -0.3v to +3.6v supply voltage, analog 3.3v (cp_vdd, cd_vdd) -0.3v to +3.6v input voltage range (aclk, wclk, ain, pclk, din) -0.5v to io_vdd+0.25v input voltage range (vco, cp_res, lf, rset) -0.5v to +3.6v input voltage range (all other pins) -0.5v to +5.25v ambient operating temperature -40c < t a < 95c storage temperature -40c < t stg < 125c peak reflow temperature (jedec j-std-020c) 260c esd sensitivity, hbm (jesd22-a114) 4000v esd sensitivity, mm (jesd22-a115) 200v notes: 1. absolute maximum ratings are those values beyond which damage may occur. functional operation under these conditions or at any other condition beyond those indicated in the ac/dc electrical characteristics sections is not implied. table 2-1: recommended operating conditions parameter symbol conditions min typ max units note s operating temperature range, ambient t a ? -20 25 85 c supply voltage, digital core core_vdd ? 1.71 1.8 1.89 v supply voltage, phase detector pd_vdd ? 1.71 1.8 1.89 v supply voltage, charge pump cp_vdd ? 3.13 3.3 3.47 v supply voltage, cable driver cd_vdd ? 3.13 3.3 3.47 v supply voltage, digital i/o io_vdd 1.8v mode 1.71 1.8 1.89 v supply voltage, digital i/o io_vdd 3.3v mode 3.13 3.3 3.47 v
gs1582 data sheet 40117 - 1 november 2007 18 of 114 2.3 dc electrical characteristics table 2-2: dc electrical characteristics guaranteed over recommended operati ng conditions unless otherwise noted. parameter symbol conditions min typ max units notes system external vco power supply voltage (vco_vdd) 2.375 2.5 2.625 v 1 +1.8v supply current i 1v8 10/20bit hd, audio enabled ? 138 165 ma 2,4 10/20bit hd, audio disabled ? 109 130 ma 2,4 10/20bit sd, audio enabled ? 112 130 ma 2,4 10/20bit sd, audio disabled ? 104 120 ma 2,4 dvb_asi ? 100 120 ma 2,4 +3.3v supply current i 3v3 10/20bit hd, audio enabled ? 74 86 ma 3,4 10/20bit hd, audio disabled ? 74 86 ma 3,4 10/20bit sd, audio enabled ? 74 86 ma 3,4 10/20bit sd, audio disabled ? 74 86 ma 3,4 dvb_asi ? 74 86 ma 3,4 to ta l d e v i c e p o w e r p d 10/20bit hd, audio enabled ? 491 600 mw 4 10/20bit hd, audio disabled ? 440 540 mw 4 10/20bit sd, audio enabled ? 445 545 mw 4 10/20bit sd, audio disabled ? 430 530 mw 4 dvb_asi ? 424 510 mw 4 reset ? 310 ? mw ? standby 10 125 ? mw 5 digital i/o input logic low v il 3.3v or 1.8v operation ? ? 0.3 x io_vdd v? input logic high v ih 3.3v or 1.8v operation 0.7 x io_vdd ??v? output logic low v ol 1.8v mode ? ? 0.3 v ? 3.3v mode ? ? 0.4 v ? output logic high v oh 1.8v mode 1.4 ? ? v ? 3.3v mode 2.4 ? ? v ?
gs1582 data sheet 40117 - 1 november 2007 19 of 114 2.4 ac electrical characteristics output output common mode voltage v cmout 75 load, rset=750 sd and hd mode ? cd_vdd - v sdd ?v? notes 1. vco_vdd guaranteed only when go1555 is connected. 2. sum of all 1.8v supplies. 3. sum of all 3.3v supplies. 4. io_vdd = 3.3v. when io_vdd = 1.8v, the current/pow er consumption is lower by up to 5ma/10mw. 5. see standby section for details. table 2-2: dc electrical characteristics (continued) guaranteed over recommended operati ng conditions unless otherwise noted. parameter symbol conditions min typ max units notes table 2-3: ac electrical characteristics guaranteed over recommended operati ng conditions unless otherwise noted. parameter symbol conditions min typ max units notes system device latency ? 10-bit sd ? ? 550 pclk ? ? 20-bit hd ? ? 1065 pclk ? ? dvb-asi ? ? 15 pclk ? ? 10-bit sd or 20-bit hd; all audio disabled ? ? 27 pclk ? reset pulse width t reset ?10??ms1 parallel input parallel clock frequency f pclk ? 13.5 ? 148.5 mhz ? parallel clock duty cycle dc pclk ?40? 60%? input data setup time t su 50% levels; 3.3v or 1.8v operation 2? ?ns 4 input data hold time t ih 2? ?ns 4 serial audio data input input data set-up time t su 50% levels; 3.3v or 1.8v operation 74 ? ? ns ? input data hold time t ih 74 ? ? ns ? serial digital output serial output data rate dr sdo ? ? 1.485 ? gb/s ? ? ? 1.485/1.001 ? gb/s ? ? ? 270 ? mb/s ? serial output swing v sdd rset = 750 75 load 750 800 850 mvp-p ? serial output rise/fall time 20% ~ 80% trf sdo hd mode ? 120 270 ps ? trf sdo sd mode 400 660 800 ps ?
gs1582 data sheet 40117 - 1 november 2007 20 of 114 mismatch in rise/fall time t r , t f ???35ps? duty cycle distortion ? ? ? 1 5 % 5 overshoot ? sd/hd =0 ? 5 10 % 5 ? sd/hd =1 ? 3 8 % 5 output return loss orl 5 mhz - 1.485 ghz ? 18 ? db 6 serial output intrinsic jitter t oj pseudorandom and smpte colour bars hd signal ?3580ps 2 t oj pseudorandom and smpte colour bars sd signal ? 100 200 ps 3 gspi gspi input clock frequency f sclk 50% levels 3.3v or 1.8v operation ??10mhz ? gspi input clock duty cycle dc sclk 40 50 60 % ? gspi input data setup time ? 1.5 ? ? ns ? gspi input data hold time ? 1.5 ? ? ns ? gspi output data hold time ? 15pf load 1.5 ? ? ns ? cs low before sclk rising edge ? 50% levels 3.3v or 1.8v operation 1.5 ? ? ns ? time between end of command word (or data in auto-increment mode) and the first sclk of the following data word - write cycle ? 50% levels 3.3v or 1.8v operation 37.1 ? ? ns ? time between end of command word (or data in auto-increment mode) and the first sclk of the following data word - read cycle ? 50% levels 3.3v or 1.8v operation 148.4 ? ? ns ? cs high after sclk rising edge ? 50% levels 3.3v or 1.8v operation 37.1 ? ? ns ? notes: 1. see ?device reset? on page 107, figure 4-33 . 2. alignment jitter = measured from 100khz to 148.5mhz 3. alignment jitter = measured from 1khz to 27mhz 4. input setup and hold time is dependent on the rise and fall time on the parallel input. parallel clock and data with rise tim e or fall time greater than 500ps require larger setup and hold times. 5. single ended into 75 external load. 6. orl depends on board design. the gs1582 achieves th is specification on g ennum?s evaluation boards. table 2-3: ac electrical characteristics (continued) guaranteed over recommended operati ng conditions unless otherwise noted. parameter symbol conditions min typ max units notes
gs1582 data sheet 40117 - 1 november 2007 21 of 114 2.5 solder reflow profiles the gs1582 is available in a pb-free package. it is recommended that the pb-free package be soldered with pb-free past e using the reflow profile shown in figure 2-1 . figure 2-1: maximum pb-free solder reflow profile 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max
gs1582 data sheet 40117 - 1 november 2007 22 of 114 3. input/output circuits all resistors in ohms, all capacitors in farads, unless otherwise shown. figure 3-1: differential output stage (sdo/sdo ) figure 3-2: charge pump current setting resistor (cp_res) cd_vdd i ref sdo sdo cp_res 200 800mv
gs1582 data sheet 40117 - 1 november 2007 23 of 114 figure 3-3: pll loop filter figure 3-4: vco input 800 800 vdd 5.6k 5.6k vdd lf 50 50 40k 160k vdd 50pf vco
gs1582 data sheet 40117 - 1 november 2007 24 of 114 figure 3-5: digital input pin with weak pull up(>33k ) (aclk[2:1], wclk[2:1], ai n[4:1], pclk, din[19:0]) figure 3-6: 5v tolerant input pin (all other input pins) figure 3-7: digital output pi n with high impedance mode (locked, audio_int, sdout_tdo) io_vdd input pin input pin io_vdd output pin en
gs1582 data sheet 40117 - 1 november 2007 25 of 114 4. detailed description 4.1 functional overview the gs1582 is a multi-rate serializer with an integrated cable driver and embedded audio multiplexer. when used in conjunction with the external go1555 voltage controlled oscillator, a transmit solution at 1.48 5gb/s, 1.485/1 .001gb/s or 270mb/s is realized. the device has three basic modes of operation that must be set through external device pins; smpte mode, dvb-asi mode, and data-through mode. in smpte mode, the device will accept 10-bit multiplexed or 20-bit demultiplexed smpte compliant data at both hd and sd signal rates. by default, the device?s additional processing features, including audio em bedding, will be enabled in this mode. in dvb-asi mode, the gs1582 will accept an 8-bit parallel dvb-asi compliant transport stream on din[ 17:10]. the serial output data stream will be 8b/10b encoded with stuffing characte rs added as per the standard. data-through mode allows for the serializing of data not conforming to smpte or dvb-asi streams. no a dditional processing will be done in this mode. in standby mode, the device pow er consumption will be reduced. the serial digital output fe atures a high impedance mode and adjustable signal swing. the output slew rate is automatically set by the sd/hd pin setting. gs1582 provides several data processing functions including generic anc insertion, smpte 352m and edh data packet generation and insertion, automatic video standards detection, and trs, crc , anc data checksum, and line number calculation and insertion. these features are all enabled/disabled collectively using the external io processing pin, but may be individually disabled via internal registers accessible through the gspi host interface. finally, the gs1582 contains a jtag interface for boundary scan test implementations.
gs1582 data sheet 40117 - 1 november 2007 26 of 114 4.2 parallel data inputs data is clocked into the device on the rising edge of pclk as shown in figure 4-1 . the input data format is defined by the setting of the external sd/hd , smpte_bypass , and dvb_asi pins and may be presented in 10-bit or 20-bit format. the input data bus width is controlled by the 20bit/10bit input pin. figure 4-1: pclk to data timing 4.2.1 parallel input in smpte mode when the device is operating in smpte mode, see smpte mode on page 28 , both sd and hd data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. in 20-bit mode, (20bit/10bit = high), the input data format should be word aligned, demultiplexed luma and chroma data. luma words should be presented on din[19:10] while chroma words sh ould be presented on din[9:0]. in 10-bit mode, (20bit/10bit = low), the input data format should be word aligned, multiplexed luma and chroma data. the data should be presented on din[19:10]. din[9:0] will be high im pedance in this mode. 4.2.2 parallel input in dvb-asi mode when operating in dvb-asi mode, see dvb-asi mode on page 34 , the gs1582 must be set to 10-bit operation mode by setting the 20bit/10bit pin low. the device will accept 8-bit data words on din[17:10]. din17 = hin is the most significant bit of the encoded transport stream data and din10 = ain is the least significant bit. in addition, din19 and din18 will be conf igured as the dvb-asi control signals inssyncin and kin respectively. see dvb-asi mode on page 34 for a description of these dvb-asi specific input signals. din[9:0] will have a logic le vel high in dvb-asi mode. pclk din[19:0] data control signal input t su t ih
gs1582 data sheet 40117 - 1 november 2007 27 of 114 4.2.3 parallel input in data-through mode when operating in data-through mode, see data-through mode on page 35 , the gs1582 passes data from the parallel input bus to the serial output without performing any encoding or scrambling. the input data bus width is controlled by the setting of the 20bit/10bit pin. 4.2.4 parallel input clock (pclk) the frequency of the pclk input signal re quired by the gs1582 is determined by the input data format. table 4-1 below lists the possible input signal formats and their corresponding parallel cl ock rates. note th at the dvb-asi input will only be in 10-bit format, when setting the 20bit/10bit pin low. table 4-1: parallel data input format input data format din [19:10] din [9:0] pclk control signals 20bit/ 10bit sd/ hd smpte_bypass dvb_asi smpte mode 20-bit demultiplexed sd luma chroma 13.5mhz high high high low 10-bit multiplexed sd luma / chroma high impedance 27mhz low high high low 20-bit demultiplexed hd luma chroma 74.25 or 74.25/ 1.001mhz high low high low 10-bit multiplexed hd luma / chroma high impedance 148.5 or 148.5/ 1.001mhz low low high low dvb-asi mode 10-bit dvb-asi dvb-asi data high impedance 27mhz low high low high low high low high data-through mode 20-bit sd data data 13.5mhz high high low low 10-bit sd data high impedance 27mhz low high low low 20-bit hd data data 74.25 or 74.25/ 1.001mhz high low low low 10-bit hd data high impedance 148.5 or 148.5/ 1.001mhz low low low low
gs1582 data sheet 40117 - 1 november 2007 28 of 114 4.3 smpte mode the gs1582 oper ates in smpte mode when the smpte_bypass pin is set high and the dvb_asi pin is set low. in this mode, the parallel data will be scrambled acco rding to smpte 259m or 292m, and nrz-to-nrzi encoded prior to serialization. 4.3.1 hvf timing in smpte mode, the gs1582 can automatically detect the video standard and generate all internal timing signals. the total line length, active line length, total number of lines per field/frame and total ac tive lines per field/frame are calculated for the received parallel video. when detect_trs is low, the video standard and timing signals are based on the externally supplied h_blanking, v_blanking, and f_digital signals. these signals go to the h/hsync, v/vsync and f/de pins respectively. when detect_trs is high, the video standard timing signals will be extracted from the embedded trs id words in the parallel input data. both 8-bit and 10-bit trs code words will be identified by the device. note: io processing must be enabled for the device to remap 8-bit trs words to the corresponding 10-bit value for transmission. see section 4.9.4.2 for more information. the gs1582 determines the video standard by timing the horizontal and vertical reference information supplied at the h/ hsync, v/vsync, and f/de input pins, or contained in the trs id words of the received video data. therefore, full synchronization to the received video standard requires one complete video frame. once synchronization has be en achieved, the gs1582 will continue to monitor the received trs timing or the supplied h, v, and f timing information to maintain synchronization. gs1582 will lose all timing information immediately following loss of h, v and f. the h signal timing should also be configured via the h_config bit of the internal ioproc_disable register as either ac tive line based blanking or trs based blanking. see packet generation and insertion on page 68 . active line based blanking is enabled when the h_config bit is set low. in this mode, the h input should be high for the entire horizontal blanking period, including the eav and sav trs words. this is the default h timing used by the device. the timing of these signals is shown in figure 4-2 .
gs1582 data sheet 40117 - 1 november 2007 29 of 114 figure 4-2: h_blanking, v_blanking, f_digital timing 4.3.2 cea 861 timing the gs1582 extracts timing information fr om externally provided hsync, vsync, and de signals when cea 861 timing mode is selected by setting detect_trs = low and the tim_861 = high. h_blanking: v_blanking: f_digital timing - hd 20-bit input mode pclk luma data out chroma data out h xyz (eav) 000 000 3ff xyz (eav) 000 000 3ff v f xyz (sav) 000 000 3ff xyz (sav) 000 000 3ff h_blanking: v_blanking: f_digital timing at sav - hd 10-bit input mode 000 000 3ff 3ff xyz (sav) 000 000 xyz (sav) pclk h v f h_blanking: v_blanking: f_digital timing at eav - hd 10-bit input mode pclk 000 000 3ff 3ff xyz (eav) 000 000 xyz (eav) multiplexed y/cr/cb data out h v f multiplexed y/cr/cb data out h_blanking: v_blanking: f_digital timing - sd 20-bit input mode pclk chroma data out luma data out h 000 3ff xyz (eav) 000 v f 000 3ff xyz (sav) 000 h_blanking: v_blanking: f_digital timing - sd 10-bit input mode multiplexed y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h signal timing: h_config = low h_config = high
gs1582 data sheet 40117 - 1 november 2007 30 of 114 horizontal sync (h), vertical sync (v), and data enable (de) timing must be provided via the h/h sync, v/vsync and f/de input pins. the host interface register bit h_config will be ignored in the cea 861 input ti ming mode. the gs1582 will determine the eia/c ea-861 standa rd and embed eav and sav trs words in the output serial video stream. video standard detection is not dependent on the hsync pulse width or the vsync pulse width and ther efore the gs1582 will tolera te non-standard pulse widths. in addition, the device can compensate for up to 1 pclk cycle of jitter on vsync with respect to hsync and sample vsync correctly. note 1: the period between the leading edge of the hsync pulse and the leading edge of data enable (de) must follow the timing requirements described in the eia/cea-861 specification. the gs1582 embeds trs words according to this timing relationship to maintain compatibility wit h the corresponding smpte standard. note 2: when cea 861 standards 6 & 7 [720(1440)x480i] are presented to the gs1582, the device will embed trs words co rresponding to the timing defined in smpte 125m to mainta in smpte compatibility. cea 861 standards 6 & 7 [720(1440)x480i] de fine the active area on lines 22 to 261 and 285 to 524 inclusive (240 active lines per field). smpte 125m defines the active area on lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1; 243 lines on field 2). therefore, in the first field, the gs1582 adds two active lines above and two active lines below the original active image. in the second field it adds two lines above and one line below the original active image.
gs1582 data sheet 40117 - 1 november 2007 31 of 114 figure 4-3: hsync:vsync:de in put timing 1280 x 720p @ 59.94/60 figure 4-4: hsync:vsync:de in put timing 1920 x 1080i @ 59.94/60 1650 cl ocks 110 hsync vsync 720 active vertical lines data enable 745 746 747 748 749 750 1 2 3 4 5 6 7 25 26 745 746 750 progressive frame: 30 vertical blanking lines 1650 total horizontal clocks per line data enable hsync 40 1280 clocks for active video 370 110 220 clocks ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2200 total horizontal clocks per line data enable hsync 44 1920 clocks for active video 280 88 148 clocks 2200 clocks 88 hsync vsync 540 active vertical lines per field data enable 1123 1124 1125 1 2 3 4 5 6 7 8 19 20 21 560 561 562 field 1: 22 vertical blanking lines 1100 2200 clocks 88 hsync vsync 540 active vertical lines per field data enable 560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125 field 2: 23 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
gs1582 data sheet 40117 - 1 november 2007 32 of 114 figure 4-5: hsync:vsync:de input timing 720 (1440) x 480i @ 59.94/60 1716 total horizontal clocks per line data enable hsync 124 1440 clocks for active video 276 38 114 clocks 1716 clocks 38 hsync vsync 240 active vertical lines per field data enable 524 525 1 2 3 4 5 6 7 8 9 21 22 261 262 263 field 1: 22 vertical blanking lines 858 1716 clocks hsync vsync data enable 261 262 263 264 265 266 267 268 269 270 271 284 285 524 525 1 field 2: 23 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ 238 238 ~ ~ ~ ~ ~ ~ ~ ~ 240 active vertical lines per field
gs1582 data sheet 40117 - 1 november 2007 33 of 114 figure 4-6: hsync:vsync:de input timing 1280 x 720p @ 50 figure 4-7: hsync:vsync:de input timing 1920 x 1080i @ 50 1980 clocks 440 hsync vsync 720 active vertical lines data enable 745 746 747 748 749 750 1 2 3 4 5 6 7 25 26 745 746 750 progressive frame: 30 vertical blanking lines 1980 total horizontal clocks per line data enable hsync 40 1280 clocks for active video 700 440 220 clocks ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2640 total horizontal clocks per line data enable hsync 44 1920 clocks for active video 720 528 148 clocks 2640 clocks 528 hsync vsync 540 active vertical lines per field data enable 1123 1124 1125 1 2 3 4 5 6 7 8 19 20 21 560 561 562 field 1: 22 vertical blanking lines 1320 2640 clocks 528 hsync vsync 540 active vertical lines per field data enable 560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125 field 2: 23 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
gs1582 data sheet 40117 - 1 november 2007 34 of 114 figure 4-8: hsync:vsync:de in put timing 720 (1440) x 576 @ 50 4.4 dvb-asi mode the gs1582 o perates in dvb-asi mode when the smpte_bypass pin is set low and the dvb_asi and sd/hd pins are set high. in this mode, all smpte processing functions are disabled, and the 8-bit transport stream data will be 8b/10b enco ded prior to serialization. 4.4.1 control signal inputs in dvb-asi mode, the din19 and din18 pi ns are configured as dvb-asi control signals inssyncin and kin respectively. when inssyncin is set high, the device w ill insert k28.5 sync characters into the data stream. this function is us ed in system implementations where the gs1582 is preceded by an external data fifo. parallel dvb-asi data may be clocked into the fifo at some rate less than 27mh z. the inssynci n input may then be connected to the fifo empty si gnal, providing a means of padding the data transmission rate to 27mhz. see figure 4-9 . 1728 total horizontal clocks per line data enable hsync 126 1440 clocks for active video 288 24 138 clocks 1728 clocks 24 hsync vsync 288 active vertical lines per field data enable 623 624 625 1 2 3 4 5 6 7 22 23 310 311 312 field 1: 24 vertical blanking lines 864 1728 clocks hsync vsync data enable 310 311 312 313 314 315 316 317 318 319 320 335 336 623 624 625 field 2: 25 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ 264 264 ~ ~ ~ ~ ~ ~ ~ ~ 288 active vertical lines per field
gs1582 data sheet 40117 - 1 november 2007 35 of 114 note: 8b/10b encoding will take place after k28.5 sync character insertion. kin should be set high whenever the paralle l data input is to be interpreted as any special character defined by the dvb- asi standard (including the k28.5 sync character). this pin should be set low when the input is to be interpreted as data. note: when operating in dvb-asi mode, din[9:0] are set to high impedance. figure 4-9: dvb-asi fifo impl ementation using the gs1582 4.5 data-through mode the gs1582 may be configured to operate as a simple parallel-to-serial converter. in this mode, the device passes data to the serial output without performing any scrambling or encoding. data-through mode is enabled only when both the smpte_bypass and dvb_asi pins are set low. 4.6 standby mode in standby mode, the power consumption of the gs1582 is reduced to 125mw. standby mode is enabled when the standby pin is set high. once the standby pin is set high, it may take up to 50ms for power reduction to take place. in this mode, the serial output pins ar e set to high impedance, and the gs1582 loses lock to the reference input pclk. while in standby mode, the programmed register values are retained. however, no registers can be accessed for reading or writing via the gspi port. no write bits will be captured and all read functions will return a value of 0. the power in standby mode can be further reduced through two means: 1. eliminate activity on all parallel data and clock inputs. this can be achieved by setting the parallel data and clock high, or not driving them. setting the parallel inputs to low is not recommended as it will result in a smaller power saving. 2. remove the 3.3v supply to the cd_vdd pin of the device. the standby power consumption under various conditions is shown in table 4-2: standby power consumption . 8 8 ain ~ hin pclk = 27mhz inssyncin sdo clk_in clk_out fifo sdo write_clk <27mhz fifo_empty ts kin gs1582 kin read clk =27mhz
gs1582 data sheet 40117 - 1 november 2007 36 of 114 in order to return to normal operation from standby mode, the standby pin must be set to low. once norm al operation is resumed, th e gs1582 will re -lock to the reference pclk. the recovery time from standby mode is the same as initial power-up but no reset is required. once the gs1582 re-locks to the reference pclk, operation is resumed according to the configuration held before entering standby mode. 4.7 audio multiplexer up to eight channels of audio may be embedded into the gs1582 video data stream in accordance with smpte 299m and smpte 272m. the audio data is input in two groups of four channels, with corresponding clock signals. the audio input signal formats supported includ e aes/ebu and three other industry standard serial digital formats. 16, 20 and 24-bit audio sample sizes are supported at 48khz synchronous for sd formats and 48khz synchronous or asynchronous for hd formats. additional audio processing features include audio mute, individual channel enable, channel re-mapping, audio group r eplacement, cascade, group selection, and audio channel status insertion. the audio system clock can be provided by gennum?s gen-clocks tm series of clock generation ic?s. in serial formats, the audio clocks required by the core are two word clocks and two signals that are a multiple of 64fs. the sd audio multiplexer core is compliant with smpte 272m a and c. the hd audio multiplexer core is fu lly compliant with smtpe 299m. 4.7.1 audio core configurations figure 4-10 shows the top level block diagrams of both the sd and hd multiplexer cores. each group of audio has one word clock signal and one audio clock signal. data present at ain_1/2 and ain_3/4 share cloc ks present at wclk1 and aclk1, while data present at ain_5/6 and ain_7/8 shar e clocks present at wclk2 and aclk2. table 4-2: standby power consumption standby condition typical power consumption (mw) standby asserted 125 standby asserted parallel data and clock inactive 100 standby asserted 3.3v supply removed from cd_vdd 35 standby asserted parallel data and clock inactive 3.3v supply removed from cd_vdd <10
gs1582 data sheet 40117 - 1 november 2007 37 of 114 audio embedding may be disabled for each group independently using the pins grp1_en/dis and grp2_en/dis . note: disabling a single group does not reduce the power consumption of the gs1582, however disabling both groups results in a power reduction. figure 4-10: audio multiplexer top level 4.7.2 audio detection the audio multiplexer detects the presence of audio data and control packets in any of four embedded audio groups. the pres ence of audio data is indicated by the adpgx_det bits in the host interface, wh ile the presence of control packets is indicated by the acpgx_det bits in the ho st interface. in sd mode, the presence of extended audio data packets is indi cated by the axpgx_det bits in the host interface. these detection flags are asserted for the duration that audio data packets are detected. for sd formats, the first ancillary data fl ag (adf) must always be contiguous after the eav words. for hd form ats, the first an cillary data flag must always be contiguous after the two eav crc words. by default, the device will delete all incoming ancillary data with audi o data or control packet did's. refer to section 4.13.3 for hd and sd audio multiplexe r status and configuration registers. sd and hd audio embedding block pclk 10 grp1_en/dis aclk1 wclk1 ain_1/2 ain_3/4 grp2_ aclk2 wclk2 ain_5/6 ain_7/8 10 audio_int reset configuration & status register read / write access audio_ins (from ioproc_dis regsiter ) ioproc_en/dis sd/hd locked _ en/dis _ _ _ _
gs1582 data sheet 40117 - 1 november 2007 38 of 114 4.7.3 audio modes of operation the audio multiplexer operates in three distinct modes: normal mode, cascade mode, and audio group replacement mode. in normal operating mode, up to two audio groups can be added to the output video. (see table 4-3: audio multiplexer modes of operation ). all existing audio packets are deleted from the video input, however arbitrary packets, sdti packets and smpte 352m packets are not deleted. when the en_cascade host interface bi t is set high, the audio multiplexer operates in cascade mode. up to two audio groups can be added to the video output. the added groups will not replace existing embedded audio groups. no existing packets are deleted from the video input, and the added audio packets are appended to the last packet in the video input. in cascade mode, if the audio multiplexer is configured to add group 1 audio data packets with the same gr oup number as an existing group, mux_erra will be asserted in the host interf ace. similarly, mux_errb will be assert ed if the configuration leads to replacing existing groups with group 2. when the agr bit in the host interface is set high, the audio multiplexer operates in group replacement mode. in this mode, added audio groups can replace existing embedded audio gr oups. the embed ded audio groups will be sorted by audio group number. no packets will be deleted fr om the video input (e xcept for the audio packets being replaced). sdti packets and smpte 352m packets are placed before the audio packets, and arbitrary packets are placed after the audio packets in sd mode. note 1: when audio group replacement mo de is selected, the cascade function is disabled. note 2: in normal sd mode, if the inco ming stream has a completely full hanc space, the outgoing hanc sp ace will only get filled with up to 235 words and the remainder of the spac e is left blank. this will not o ccur if there ar e one or more words free in the incoming hanc space. note 3: sd audio in cascade mode may on ly be inserted if the hanc space of the incoming stream is not completely full. if the incoming stream has a full hanc space, audio packets will be inserted beyond the hanc boundary . the space following the inserted audi o packets will then be blanke d until the next eav is detected in the video stream . this will not occur if there are two or more words free at the end of the incoming hanc space after the existing packets. note 4: hd audio in normal mode may on ly be inserted if the hanc space of the incoming stream is not co mpletely full. if the inco ming stream has a full hanc space, packets will be in serted beyond the hanc bo undary. the space following the inserted pack ets will then be blanked until the next eav is de tected in the video stream. this will not occur if there are two or more words free at the end of the incoming hanc space after the existing packets.
gs1582 data sheet 40117 - 1 november 2007 39 of 114 4.7.4 audio packet delete ancillary data packets with no n-audio data id words, such as arbitrary, edh, sdti header and smpte 352m, will not be deleted from the data stream. on lines where smpte 352m or sdti header packets exist, the audio data packets must be contiguous to the 352m and sdti packets in sd mode. for hd formats, the audio data packets must always be contiguous after the two eav crc words. if this is not the case, all existing audio data and control packets will be deleted. when the en_cascade host interface bit is set high, all existing audio data and control packets will remain in the video stream. when the agr bit in the host interface is set high, audio group replacement mode is selected. in this mode, existing audio data and cont rol packets will no t be deleted from the data stream with the exception of any packets of groups being replaced. in cases where the adf is not placed immediately afte r the crc or eav words, or there are gaps between the packets, the audio core will delete all existing audio data and control packets, regardless of the en_cascade or agr setting. figure 4-11 shows an example of correct and in correct placement of ancillary data packets for a sd format. figure 4-11: ancillary data packet placement example table 4-3: audio multiplexer modes of operation host interface registers operating mode en_cascade = 0, agr = 0 normal mode en_cascade = 1, agr = 0 cascade mode en_cascade = 0, agr = 1 audio group replacement mode en_cascade = 1, agr = 1 audio group replacement mode blank blank blank eav hanc with space between eav and ancillary data (audio packets will be deleted) sav audio group 1 audio group 2 correct placement of ancillary data within hanc space blank eav sav audio group 1 audio group 2 352m / sdti packet 352m / sdti packet
gs1582 data sheet 40117 - 1 november 2007 40 of 114 4.7.5 arbitrary, smpte 352m & edh packet detect the audio multiplexer detects the presence of any arbitrary data packets. if present, these packets will be removed and stored for re-insertion after audio packets have been embedded. if there is insufficient hanc space available, the arbitrary data packe t will be discarded. to detect the arbitrary da ta packet, the audio core looks for any ancillary data packets which have a did other than audio, extended audio, control, sdti header, smpte 352m or edh packets. arbitrary data packets and formatting are defined in smpte 291m. arbitrary data packets are only present on the luma channel of the hd video input. all edh processing is carried out following the audio core, as the crc's will require updating. the audio core detects the presence of edh packets in the hanc region. these packets are preserved and re-embedded after multiplexing of audio packets, according to rp 165. the audio core does not perform edh crc calculation and flag updates. since the audio core multiple xes audio packets on to lines where the ancillary data packet containing edh checkwords and stat us flags is to be placed (lines 9 and 272 in 525, and lines 5 and 318 in 625), if there is insufficient horizontal ancillary data space available after audio multip lexing, the edh block will overwrite audio packets. this problem may occur in both 525 and 625 when 16 channels (4 audio groups) of 24-bit audio are embedded. note 1: the audio sample distribution used by the sd audio core for both 525 and 625 will increase the available space in the horizontal anc illary data space. note 2: due to the large size of the hor izontal ancillary data space in 720p/24, 720p/25 and 720 p/30 video sta ndards, the maxi mum number of ancillary data words the audio core can process is limited to 1024 when configured to these standards. table 4-4 lists the data id's and packet leng ths for arbitrary, edh, sdti header and smpte 352m packets. when the presence of a smpte 352m packet is detected, the audio core extracts and stores the packet for re-insertion. audio data packets will always be placed after the smpt e 352m packet. table 4-4: non-audio ancillary data packet dids ancillary data packet did sdid packet length (words) arbitrary (smpte 291m) user user 262 max edh (rp 165) 1f4h ? 23 payload identifier (smpte 352m) 241h 101h 11 sdti header (smpte 305m) 140h 101h 53
gs1582 data sheet 40117 - 1 november 2007 41 of 114 note: when serializing sdti signals, it is recommended that the user ensure there are no smpte 352m packets present in the input video data. 4.7.6 audio packet multiplexing the sd core places audio data packets contiguously after the eav. any extended audio data packets are placed immediately following the audio data packet of the same audio group. the hd core places audio data packets contiguously after the two line crc words. in cases where the smpte 352m packet or sdti header are present after the eav or crc, the audio data will be placed co ntiguously from the 3 52m or sdti header packets. on lines where the 352m or sdti header packets are present, there may be insufficient hanc space for embedding 4 audio groups. if there is insufficient hanc space available, the 352m or sdti header packets are always re-inserted and the remaining audio group packet to be inserted is discarded. on lines where the edh packet is present, the audio data will be embedded up to the point reserved for the edh packet. if there is insufficient hanc space available, the edh packet is always re-inserted and the audio data packet discarded. in the case where there is insufficient room in the hanc space to embed the selected audio data packets, the multiple xer core will delete any arbitrary data packets. if there is still insu fficient room in the hanc space, the multiplexer core will not embed audio data packets. 4.7.7 audio insertion afte r video switching point 4.7.7.1 sd formats the switching lines for sd formats are defined in smpte rp 168 as lines 10 and 273 for 525-line based formats, and lines 6 and 319 for 625-line based formats. the audio core does not place any audio data or control packets in the line immediately after the video switching line. for example, with the standard switch point of line 10 for field 1 in 525, there will be no audi o data or control packets on line 11. the next packets will appear on line 12. 4.7.7.2 hd formats the video switching lines for hd formats are defined in smpte 299m as lines 7 and 569. the audio core does not place any audio data or control packets in the line immediately after the video switchin g point. for example, with the standard switch point of line 7 for fi eld 1, there will be no audio da ta packets in line 8. the next packets will appear on line 9. th e audio control packets will be multiplexed once per field, two lines after the video switch point, on lines 9 and 571.
gs1582 data sheet 40117 - 1 november 2007 42 of 114 4.7.8 audio data packets 4.7.8.1 sd formats figure 4-12 shows the structure of the sd audio data packet as defined in smpte 272m. table 4-5 lists the descriptions of the au dio data packet words. the audio core automatically generates certain audio data packet words, as shown in table 4-5 . figure 4-12: sd audio data packet structure figure 4-13 shows the structure of the extended audio data packets as defined in smpte 272m. table 4-6 lists the descriptions of the extended audio data packet words. the audio core automatically generates certain audio data packet words. the extended audio data packet is em bedded immediately after the audio data packet with same group did. adf audio sample words 10-bit did dbn dc ch1 ch2 ch3 ch4 cs x x+1 x+2 x x+1 x+2 x x+1 x+2 x x+1 x+2 x x+1 x+2 x x+1 x+2 ch3 ch4 table 4-5: audio data packet word descriptions name no. of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 2ffh 1fdh 1fbh 2f9h see table 4-10 dbn 1 data block number repeat 1-255 yes dc 1 data count ? yes ch1 4 channel 1 ancillary data words ? ch2 4 channel 2 ancillary data words ? ch3 4 channel 3 ancillary data words ? ch4 4 channel 4 ancillary data words ? cs 1 checksum ? yes
gs1582 data sheet 40117 - 1 november 2007 43 of 114 figure 4-13: sd extended audi o data packet structure for both audio data and extended audio packets, the data block number is embedded with a running sequence of 1 to 255. 4.7.8.2 hd formats figure 4-14 shows the structure of the audio data packets as defined in smpte 299m. the audio data packets are multiplexed into the chroma channel of the video data stream. table 4-7 lists the descriptions of th e audio data packet words. the audio core automatically generates certai n audio data packet words, as shown in table 4-7 . figure 4-14: hd audio data packet structure adf extended audio 10-bit did dbn dc aux aux aux aux cs aux aux aux aux aux aux aux aux aux aux aux aux aux aux table 4-6: extended audio data packet word descriptions name no. of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 1feh 2fch 2fah 1f8h see table 4-10 dbn 1 data block number repeat 1-255 yes dc 1 data count ? yes aux 4 auxiliary data from one channel pair words ? cs 1 checksum ? yes adf user data words ecc0 10-bit did dbn dc clk ch1 ch2 ch3 ch4 ecc1 ecc2 ecc3 ecc4 ecc5 cs ecc protected
gs1582 data sheet 40117 - 1 november 2007 44 of 114 table 4-7: audio data packet word descriptions name no. of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 2e7h 1e6h 1e5h 2e4h see table 4-10 dbn 1 data block number repeat 1-255 yes dc 1 data count 218h yes clk 2 audio clock phase data ? yes ch1 4 channel 1 ancillary data words ? ch2 4 channel 2 ancillary data words ? ch3 4 channel 3 ancillary data words ? ch4 4 channel 4 ancillary data words ? ecc0-5 6 error correction code for lower 8 bits of first 24 words ?yes cs 1 checksum. calculates the sum of lower 9 bits of 22 words from did ?yes
gs1582 data sheet 40117 - 1 november 2007 45 of 114 4.7.9 audio control packets 4.7.9.1 sd formats in sd mode, the cont rol packets are inserted in the first line after the blanking line, and following the audio data packets. figure 4-15 shows the structure of the sd audio control packet as defined in smpte 272m. an audio control packet is mu ltiplexed once per field in the video data stream. table 4-8 lists descriptions of the aud io control packet words. the audio core automatically generates certain audio control packet words. figure 4-15: sd audio control packet structure table 4-8: audio control packet word descriptions name no. of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 1efh 2eeh 2edh 1ech see table 4-10 dbn 1 data block number repeat 1-255 yes dc 1 data count ? yes af1-2 1 ch1/2 audio frame number ? yes af3-4 1 ch3/4 audio frame number ? same as af1-2 rate 1 sampling frequency ? yes act 1 active channel ? act[8:1] setting dela0 -3 3 ch1/ch1&2 delay data ? 27-bit host interface setting delb0 -3 3 ch3/ch3&4 delay data ? 27-bit host interface setting delc0 -3 3 ch2 delay data ? 27-bit host interface setting deld0 -3 3 ch4 delay data ? 27-bit host interface setting adf user data words 10-bit did dbn dc af1-2 dela0-3 delb0-3 cs rate act af3-4 delc0-3 deld0-3 rsrv rsrv
gs1582 data sheet 40117 - 1 november 2007 46 of 114 4.7.9.2 hd formats in hd mode, the control packets are inserted in the first line after the blanking line in the luma channel in the first available space. figure 4-16 shows the structure of the hd audio control packet as defined in smpte 299m. an audio control packet is mu ltiplexed once per field in the luma channel of the video data stream. table 4-9 lists descriptions of the individual audio control packet words. the aud io core automatically gene rates certain audio control packet words. figure 4-16: hd audio control packet structure rsrv 2 reserved words 200h yes cs 1 checksum. calculates the sum of lower 9 bits of 22 words from did ?yes table 4-8: audio control packet word descriptions (continued) name no. of words description data auto-generation table 4-9: audio control packet word descriptions name no. of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 1e3h 2e2h 2e1h 1e0h see table 4-10 dbn 1 data block number 200h yes dc 1 data count 10bh yes af 1 audio frame number ? yes rate 1 sampling frequency ? yes act 1 active channel ? act[8:1] setting dela0-3 3 ch1/2 delay data ? 27-bit host interface setting adf user data words 10-bit did dbn dc af del1-2 del3-4 rsrv cs rate act
gs1582 data sheet 40117 - 1 november 2007 47 of 114 4.7.9.3 audio control packet insertion to multiplex audio control packets for audio group 1 channels 1 to 4 (inputs ain_1/2 and ain_3/4), the ctra_on bit of the host interface must be set high. to multiplex audio control packe ts for audio group 2 channels 5 to 8 (inputs ain_5/6 and ain_7/8), the ct rb_on bit must be set high. in addition, the multiplexer will only embed or replace group 1 control packets if one or more of act1, act2, act3 and act4 are set. si milarly, group 2 control pa ckets will only be embedded or replaced if act5, act6, act7 or act8 are set. by default, the audio control packets ar e embedded. the audio frame sequence is also embedded for 29.97fps video st andards. setting the afna_auto and afnb_auto bits in the host interface low disable the audio frame sequence insertion. when set low, the audio frame number will be set to zero (200h). the rate word is always set to zero to denote 48khz audio only. control packet data can be programmed via the corresponding registers in the host interface. refer to section 4.13.3 for hd and sd audio multiplexe r status and configuration registers. 4.7.10 setting packet did the audio group did for audio group 1 input channels 1 to 4 (ain_1/2 and ain_3/4) is set in the ida[1:0] bits of the host interface. the audio group did for audio group 2 input channels 5 to 8 (ain_5/6 and ain_7/8) is set in idb[1:0] of the host interface. table 4-10 shows the 2-bit host interface setting for the corresponding audio group did. for 24-bit audio support using the sd core, the extended audio group did for audio group 1 input channels 1 to 4 is set to the same group in ida[1:0] of the host interface. the extended audio group did fo r audio group 2 input channels 5 to 8 is set to the same group in idb[1:0] of the host interface. 24-bit support is selected by setting the 24bit bit of host interface high. when the host interface cascade bit is se t low, the audio core defaults to audio groups 1 and 2, where ain_1/2 and ain_ 3/4 are multiplexed with audio group 1 did, and ain_5/6 and ain_7/8 with audio group 2 did. delb0-3 3 ch3/4 delay data ? 27-bit host interface setting rsrv 2 reserved words 200h yes cs 1 checksum. calculates the sum of lower 9 bits of 15 words from did ?yes table 4-9: audio control packet word descriptions (continued) name no. of words description data auto-generation
gs1582 data sheet 40117 - 1 november 2007 48 of 114 when the cascade bit is set high, the gs1582 defaults to audio groups 3 and 4, where ain_1/2 and ain_3/4 are multiple xed with audio group 3 did, and ain_5/6 and ain_7/8 with audio group 4 did. note: if ida and idb are set to the same value, these bits will automatically revert to their default values. any other configurations can be programme d for the audio groups as required. 4.7.11 audio group replacement audio group replacement mode allows the multiplexing of new audio groups, whilst replacing existing embedded audio with the same group did. all other embedded audio groups will remain in the video str eam. up to two grou ps of audio (and extended audio for sd formats) can be replaced at once. the first function performed by the gs1582 is deleting the audio group or groups to be replaced. the next step is removi ng and storing any other audio packets that are to be preserved. the final step is to embed the new and stored audio data packets so they are cont iguous from the eav (for hd formats, they will be contiguous after the line crc words). see figure 4-17 . table 4-10: audio group did host interface settings audio group sd data did sd extended did hd data did sd control did hd control did host interface register setting (2-bit) 1 2ffh 1feh 2e7h 1efh 1e3h 00b 2 1fdh 2fch 1e6h 2eeh 2e2h 01b 3 1fbh 2fah 1e5h 2edh 2e1h 10b 4 2f9h 1f8h 2e4h 1ech 1e0h 11b table 4-11: audio data and contro l packet did setting register name description default cascade set low default cascade set high ida[1:0] group 1 audio data and control packet did setting 00b 10b idb[1:0] group 2 audio data and control packet did setting 01b 11b
gs1582 data sheet 40117 - 1 november 2007 49 of 114 on lines where the smpte 352m packet is al ready present, the audio core places new and existing audio data packets cont iguously after the 352m packets. for hd formats, the 352m packets are embedded in the luma channel of the video data stream; theref ore, no audio data pa ckets will be placed a fter the 352m packets. figure 4-17: audio group replac ement example (hd formats) audio group replacement mode is selected by setting the agr bit of the host interface high. by default, the gs1582 r eplaces two audio gr oups with their did set in ida[1:0] and idb[1:0]. to replace only one audio group, with group did set in ida[1:0], set the one_agr bit in the host interface high . the audio control packets, if present, will not be replaced unless the ctr_agr ho st interface bit is set high. the audio control packet in formation will be replaced with data programmed in the associated registers in the host interface. see audio control packets on page 45 . refer to section 4.13.3 for hd and sd multiplexer core status and configuration registers. blank (200 h ) video signal input to audio core (with existing audio data packets) blank (200 h ) eav video signal after deleting audio groups 1 & 2 (one_agr = 0) sav audio group 3 audio group 4 ln crc blank (200 h ) eav video signal output after replacement of audio groups 1 & 2 sav audio group 1 (new) audio group 2 (new) audio group 3 (old) audio group 4 (old) ln crc blank (200 h ) eav sav audio group 1 audio group 2 audio group 3 audio group 4 ln crc blank (200 h ) eav video signal after audio groups 3 & 4 stored in ram sav ln crc
gs1582 data sheet 40117 - 1 november 2007 50 of 114 4.7.12 channel and group activation multiplexing of individual audio channels is enabled by setting the actn bits in host interface register 0ch. when set high, the corresponding audio channel is multiplexed into the video data stream. channels designated as not active (actn set low) will be embedded with null samples (all bits set to zero). when all actn bits are set low, no audio data packets will be multiplexed. when act[1-4] are set low, the audio group set in ida[1:0] will not be multiplexed. similarly, when act[5-8] are set low, the audio group set in idb[1:0] will not be multiplexed. this allows four channel, single group operation. by default, all audio channels are enabled. refer to section 4.13.3 for hd and sd audio multiplexe r status and configuration registers. 4.7.13 ecc error detection & correction (hd mode only) the gs1582 will generate the error detection and correction fields in the audio data packets. all generated error detection and correction complies with smpte 299m. 4.7.14 interrupt control the gs1582 can be programmed to assert the interrupt signal (audio_int, pin h7) whenever an internal interrupt condition exists. to enable a particular type of interrupt, the corresponding bit in the host interface must be set. if the audio interrupt bit is un-masked, and the interrupt condition is met, the the audio_int pin will go high . for example, if the en_adpg_1 is enabled, and the incoming video has emb edded audio in group one, then the audio_int pin will go high. please refer to section 4.13.3 for hd and sd audio multiplexer status and configuration registers for a complete listing of the audio interrupts. 4.7.15 audio clocks the audio multiplexer has 4 clock inputs: aclk_1, aclk_2, wclk_1 and wclk_2. for serial audio input modes aclk_1/2 must be provided at 64fs, where fs is the fundamental sampling frequency of 48khz. an audio word clock at 48khz must also be supplied at the wclk_1/2 inputs. for aes/ebu audio input mode, the aclk_1/2 and wlck_1/2 inputs are no t required. all required clocks will automatically be derived from the aes/ ebu preambles. aclk_1/2 and wclk_1/2 will be high impedance in aes/ebu audio input mode.
gs1582 data sheet 40117 - 1 november 2007 51 of 114 figure 4-18: aclk to data & control signal input timing 4.7.16 5-frame sequence detection 5-frame sequence detection is requir ed for 525-line based standard definition formats and to embed the audio frame number word in the audio control packets for synchronous audio in both hd and sd formats. 4.7.16.1 sd audio multiplexing the gs1582 detects the frame sequence that describes the sample distribution for synchronous audio. this information is us ed in the generation of the audio frame number (afn) field, describing the pos ition of the current frame within the sequence. afn values will only be generat ed for group a if the afna_auto bit in the host interface, and for group b if the afnb_auto bit is set. if the gs1582 is not configur ed to generate afn values , the afn field will be set to 0 at all times. however, if the core is configured to generate afn values, the afn value will be between 1 and 5, depending on where the given frame lies in the frame sequence. with a frame rate of 25 hz, each frame will contain 1920 samples, and each frame will have an afn of one (see table 4-13 ). for a frame rate of 29.97 hz, 8008 samples are distributed over 5 frames, as shown in table 4-14 . the gs1582 will add the offset specified in the afn_ofs[2:0] ho st interface field to the generated afn. the result will wrap around, le aving the resulting afn in the range of 1 through 5. table 4-12: gs1582 serial audio data inputs parameter symbol conditions min typ max units input data set-up time t su 50% levels; 3.3v or 1.8v operation 74 ? ? ns input data hold time t ih 74 ? ? ns aclk a_in_[8/7:2/1] data control signal input t su t ih data
gs1582 data sheet 40117 - 1 november 2007 52 of 114 4.7.16.2 hd audio multiplexing if the asxa bit of the host in terface is set to asynchr onous audio, the gs1582 will set the afn of the group 1 control packet s to zero. the gs1582 will also set the afn of the group 1 control packets to zero if the afna_auto bit in the host interface is not set. the same relationship holds for the asxb and afnb_auto bits for group 2. the gs1582 will detect video standards with 29.97 and 59 .94 frame rates by using the 5-frame sequence detect block. if a 5-frame sequence is detected, the audio frame number word in the audio co ntrol packets will be embedded with the running sequence 1 through 5. the gs1582 will add the offset specified in the afn_ofs[2:0] ho st interface field to the generated afn. the result will wrap around, le aving the resulting afn in the range of 1 through 5. in cases where each frame has the same number of samples, the multiplexer will set the afn to zero for every frame. these cases are shown in table 4-13 . in cases where each frame has a different nu mber of samples, the sequences shown in table 4-14 are used. 4.7.17 audio input format the gs1582 accepts two audio input fo rmats, aes/ebu digita l audio input and serial digital audio input, as listed in table 4-15 . the serial audio input can be formatted in the fo llowing five modes: table 4-13: frame rates with afn = 0 frame rate (fps) samples per video frame 30 1600 25 1920 60 800 24 2000 23.98 2002 table 4-14: frame rates with varying samples per frame frame rate (fps) samples, afn = 1 1 samples, afn = 2 1 samples, afn = 3 1 samples, afn = 4 1 samples, afn = 5 1 29.97 1602 1601 1602 1601 1602 59.94 801 800 801 801 801 notes: 1. afns are assuming afn_ofs = 0.
gs1582 data sheet 40117 - 1 november 2007 53 of 114 ?i 2 s ? left justified; msb first ? left justified; lsb first ? right justified; msb first ? right justified; lsb first the audio input format for each audio gr oup is configured using the ama[1:0] (group 1 channels 1 and 2/stereo pair a), amb[1:0] (group 1 channels 3 and 4/stereo pair b), amc[1:0] (group 2 ch annels 5 and 6/stereo pair c), and amd[1:0] (group 2 channels 7 and 8/stereo pair d) host interface registers. the default audio mode is i 2 s input. for serial input formats, msb first is default, and lsb first is available via the lsb_firstx bit in the host interface. note: since the audio clocks are common to all channels within one group, all channels in each group of four must be the same format. ho wever there is no restriction on the format of different channels in one group when audio is in aes/ebu format. also, the audio format of each group may be different. 4.7.17.1 aes/ebu mode in aes/ebu input mode, the audi o sample bit rate of 64fs (3.072mhz) is effectively doubled by the bi-phase mark encoding, resu lting in an effective input data rate at 128fs (6.144mhz). the aes/ebu sub- frame formatting is shown in figure 4-19 below. table 4-15: audio input formats amx[1:0] lsb_firstx audio output format 00 0 aes/ebu audio input 01 0 serial audio input: left justified; msb first 01 1 serial audio input: left justified; lsb first 10 0 serial audio input: right justified; msb first 10 1 serial audio input: right justified; lsb first 11 0 i 2 s serial audio input (default)
gs1582 data sheet 40117 - 1 november 2007 54 of 114 figure 4-19: aes/ebu su b-frame formatting the audio clock to data timing and input format is shown in figure 4-20 . figure 4-20: aes/ebu audio input format note: due to the bi-phase mark encoding used in aes/ebu mode, for each logic 1 bit period, there will be an additional transition. in figure 4-20 , this additional transition is not shown. in the event of a parity error in stereo pair a in aes/ebu mode, the gs1582 will set the aes_erra bit in the host interfac e. the same is true of aes_errb for stereo pair b, aes_errc for stereo pair c, and aes_errd for stereo pair d. note: in order to read back the parity error bits of register 1, register 2 must be read first to trigger an update of these bi ts. the parity error bits will be cleared when read from register 1. 4.7.17.2 serial audio input mode in serial audio input modes, the gs1582 clocks the audio data input on the rising edge of the aclk_1/2 input clock at 64fs (3.072mhz), as shown in figure 4-21 , figure 4-24 and figure 4-25 below. figure 4-21: serial audio input: left justified; msb first 24 -bit sync preamble 24-bit audio sample word vucp 034 27 2 8 29 30 31 channel status bit validity bit user data bit parity bit 20-bit sync preamble 20-bit audio sample word vucp 034 27 2 8 29 30 31 lsb msb lsb msb 7 8 aux data 16-bit sync preamble 16-bit audio sample word vucp 034 27 2 8 29 30 31 lsb msb 7 8 aux data 11 12 set to zero ain msb 2 8 27 8 7 2 1 0 lsb 3456 29 30 31 vucp aux preamble msb 2 8 27 8 7 2 1 lsb 3456 29 30 31 vucp aux preamble 0 wclk aclk ain 23 msb 22 0 1 2 3 4 5 6 21 lsb 23 msb 22 0 1 2 3 4 5 6 21 lsb channel a (left) channel b (right)
gs1582 data sheet 40117 - 1 november 2007 55 of 114 figure 4-22: serial audio input: left justified; lsb first figure 4-23: serial audio input: right justified; msb first figure 4-24: serial audio input: right justified; lsb first figure 4-25: i 2 s audio input 4.7.18 audio channel status input the audio channel status block informa tion can be programmed via the host interface using the acsr [183:0] register (see table 4-17: audio channel status information register settings ). the audio channel stat us input consists of 24 bytes transmitted 1 bit per audio sample over a 192-frame sequence. the same audio channel status information is embe dded for each sample in an audio frame, over all 8 input channels. the gs1582 genera tes the z bit to denote the start of the audio channel status block. when the acs_regen bit in the host in terface is set high, the gs1582 will use the audio channel status information prog rammed in the acsr[183:0] register to replace the audio channel status block in all eight channels. the crc for the audio channel status block will be calc ulated automatically. the gs1582 will use this new audio channel st atus information only when acs_apply is high and a new status boundary at this point. when the acs_apply is set, the apply_waita host interface bit will be as serted until a status boundary for audio wclk aclk ain 0 lsb 123 22 21 20 19 18 17 2 msb lsb msb channel a (left) channel b (right) 01 23 22 21 20 19 18 17 2 wclk aclk ain 23 msb 22 0 1 2 20 17 1 8 19 21 lsb msb lsb channel a (left) channel b (right) 23 22 0 1 2 20 17 1 8 19 21 wclk aclk ain 0 lsb 123 22 21 36 5 4 2 msb 0 lsb 123 22 21 36 5 4 2 msb channel a (left) channel b (right) wclk aclk ain 23 msb 22 0 1 2 3 4 5 6 7 lsb 23 msb 22 0 1 2 3 4 5 6 7 lsb channel a (left) channel b (right)
gs1582 data sheet 40117 - 1 november 2007 56 of 114 group 1 occurs. simila rly, apply_waitb will be asserted starting when acs_apply is set, and ending when a stat us boundary for audi o group 2 occurs. table 4-16 shows the default settings for t he audio channel status block. the gs1582 automatically generates the crc byte. 4.7.19 audio crosspoint the audio crosspoint allows any single input channel to be embedded as one or more of the 8 embedded audio channels. the default setting is for one-to-one mapping, where ain_1/2 is embedded as ch1 and ch2, ain_3/4 is embedded as ch3 and ch4, and so on. the same audio channel cannot be used in both group 1 and 2 at the same time. the gs1582 will assert the xpoint_erro r host interface bit if any audio channel is programmed to be included in both groups. table 4-16: audio channel stat us block default settings name byte bit default mode pro 0 0 1b professional use of channel status block emphasis 0 2-4 100b none. receiver manual override disabled sample frequency 0 6-7 01b 48khz. manual override or auto disabled channel mode 1 0-3 0001b two channels. manual override disabled aux 2 0-2 000b sd mode: maximum audio word length is 20 bits 001b hd mode: maximum audio word length is 24 bits source word length 2 3-5 101b maximum word length (based on aux setting). 24-bit for hd formats; 20-bit for sd formats table 4-17: audio channel status information register settings name description default acsr[7-0] audio channel status block byte 0 set 85h acsr[15-8] audio channel status block byte 1 set 08h acsr[23-16] audio channel status block byte 2 set 28h (sd) 2ch (hd) acsr[31-24] acsr[183-176] audio channel status block set for bytes 3 to 22 00h
gs1582 data sheet 40117 - 1 november 2007 57 of 114 the source channel is set via the host interface. table 4-18 lists the 3-bit address for audio channel mapping. note: audio channels can be paired only when both channels are derived from the same word clock and are synchronous. 4.7.20 audio word clock the gs1582 uses two word clocks, wclk_1 and wclk_2. by default, audio group 1 will use the clock at the wclk_1 in put, and audio group 2 will use the word clock at wclk_2. the word clock assignment for each audio group can be changed by programming the gp1_wclk_src[1:0] and gp2_wclk_src[1:0] registers. in aes mode, the audio clocks are extracted from the inpu t audio data. by default, audio clock for group 1 is extracted from channel pair 1/2, and audio clock group 2 is extracted from channel pair 5/6. th e default can be changed by programming table 4-18: audio channel mapping codes audio input channel 3-bit host interface source address group 1 channel 1 000b group 1 channel 2 001b group 1 channel 3 010b group 1 channel 4 011b group 2 channel 1 100b group 2 channel 2 101b group 2 channel 3 110b group 2 channel 4 111b table 4-19: source input address registers name description default gp1_ch1_src[2:0] group 1 channel 1 source selector 000b gp1_ch2_src[2:0] group 1 channel 2 source selector 001b gp1_ch3_src[2:0] group 1 channel 3 source selector 010b gp1_ch4_src[2:0] group 1 channel 4 source selector 011b gp2_ch1_src[2:0] group 2 channel 1 source selector 100b gp2_ch2_src[2:0] group 2 channel 2 source selector 101b gp2_ch3_src[2:0] group 2 channel 3 source selector 110b gp2_ch4_src[2:0] group 2 channel 4 source selector 111b
gs1582 data sheet 40117 - 1 november 2007 58 of 114 the gp1_wclk_src[1:0] and gp2_wclk_src[1:0] register. table 4-20: audio clock selection host interface settings shows the audio clock source for each setting of the registers. each audio group consists of 4 channels, which share the same word clock. therefore, the audio data applied to each channel within the group must be the same format and have identical word clock requirements. note: in aes mode, by default, word cloc k is extracted from channels 1/2 for audio group 1 and channels 5/6 for audio gro up 2. if audio is applied only to 3/4 or 7/8 only, then no audio is embedded until the word clock source is changed from channels 1/2 or 5/6, to channels 3/4 or 7/8. 4.7.21 gs1582 sd audio fifo block the gs1582 sd audio fifo block contains the audio sample buffers. there is a buffer per audio channel, which are 52 audio samples deep. at power up or reset, the read pointer is held at the zero position until 26 samples have been written into the fifo. once audio is being multiplexe d, the offset between the audio sample buffer read and write pointers is maintained at an average of 26 samples. the position of the write pointer with respect to the read pointer is checked constantly. if the write pointer is less than 6 samples ahead of the read pointer, a sample is repeated from the read-side of the buffer. if the write pointer is less than 6 samples behind the read pointer, a sample is dropped. this scheme avoids buffer underflow/overflow conditions. the repeat or drop sample operation is performed up to a maximum of 28 consecutive times. after 28 repeat/drops, the gs1582 will mute (null audio packets are embedded). the audio buffer pointer offset can be reduced from 26 samples to 12 or 6 samples using the os_sel[1:0] host interface register. the default setting is 26 samples (see table 4-21 ). when the os_sel[1:0] bits are set for 6-sample pointer offset, no boundary checking is performed. table 4-20: audio clock selection host interface settings gp_wclk_src[1:0] word clock extraction source (aes mode) wclk source (serial audio mode) 00b channels 1/2 wclk_1 01b channels 3/4 wclk_1 10b channels 5/6 wclk_2 11b channels 7/8 wclk_2
gs1582 data sheet 40117 - 1 november 2007 59 of 114 the clear_audio bit in the host interfac e can be used to clear the fifos. when asserted, this bit resets the fifos to the start-up state. 4.7.22 audio sample distributions 4.7.22.1 525-line audi o sample distribution this following sample distribution allows the embedding of 16 channels (4 audio groups) of 24-bit sampled audio into the hanc of 525-line based video formats. the sample distribution is established for group 1 and then offset by 1 line for each subsequent group. the sample distribution is as follows (start line is 12): {[3] (10+g) ,([4],[3] 15 ) 15 ,[4],[3] (11-g) ,[0],[3] (3+g) ,([4],[3] 15 ) 15 ,[4/3],[3] 12 ,[4],[3] (4-g) ,[0]} 5 [#] = number of samples / line [4/3] = one line with either 3 or 4 samples depending on five-frame sequence (#) = number of times to repeat the sequence. when this # is 0, no samples are inserted g = audio group number from 1 to 4 {?} 5 = 5-frame sequence as shown in table 4-22 : table 4-23 , table 4-24 , table 4-25 , and table 4-26 show the audio sample distributions for each of the four audio groups. each distribution has 525 lines with either 1602 or 1601 samples based on the frame number of the five-frame sequence. table 4-21: audio buffer pointer offset settings os_sel[1:0] buffer pointer offset 00 26 samples (default) 01 12 samples 10 6 samples table 4-22: 5-frame sequence sample distribution frame number of samples 1 1602 2 1601 3 1602 4 1601 5 1602
gs1582 data sheet 40117 - 1 november 2007 60 of 114 note: when 1602 samples are required, the [4/3] term represents a line with 4 samples. when 1601 samples are required, the [4/3] term represents a line with 3 samples. 4.7.22.2 625-line audi o sample distribution the following sample distribution is for 62 5-line video standards which leaves more free hanc space when inserting 16 channe ls (4 audio groups) of 24-bit sampled audio. the sample distribution is established for group 1 and then offset by 1 line for each subsequent group. the sample distribution is as follows (start line is 8): [3] (g-1) ,([4],[3] 11 ) 25 ,[4],[3] (12-g) ,[0], [3] (g-1) ,([4],[3] 11 ) 24 ,[4],[3] (23-g) ,[0] [#] = number of samples / line (#) = number of times to repeat the sequence table 4-23: group 1 audio sample distribution [3] (10+1) ([4],[3] 15 ) 15 [4],[3] (11-1) [0],[3] (3+1) ([4],[3] 15 ) 15 [4/3],[3] 12 [4],[3] (4-1) ,[0] samples 33 735 34 12 735 40 / 39 13 lines 11 240 11 5 240 13 5 table 4-24: group 2 audio sample distribution [3] (10+2) ([4],[3] 15 ) 15 [4],[3] (11-2) [0],[3] (3+2) ([4],[3] 15 ) 15 [4/3],[3] 12 [4],[3] (4-2) ,[0] samples 36 735 31 15 735 40 / 39 10 lines 12 240 10 6 240 13 4 table 4-25: group 3 audio sample distribution [3] (10+3) ([4],[3] 15 ) 15 [4],[3] (11-3) [0],[3] (3+3) ([4],[3] 15 ) 15 [4/3],[3] 12 [4],[3] (4-3) ,[0] samples 39 735 28 18 735 40 / 39 7 lines 13 240 9 7 240 13 3 table 4-26: group 4 audio sample distribution [3] (10+4) ([4],[3] 15 ) 15 [4],[3] (11-4) [0],[3] (3+4) ([4],[3] 15 ) 15 [4/3],[3] 12 [4],[3] (4-4) ,[0] samples 42 735 25 21 735 40 / 39 4 lines 14 240 8 8 240 13 2
gs1582 data sheet 40117 - 1 november 2007 61 of 114 [3] (0) = no lines with no samples g = audio group number from 1 to 4 note: for audio group 1, the [3] (g-1) terms are 0 (zero) and lines 8 and 321 start with the 4 samples of the ([4],[3] 11 ) 25 and ([4],[3] 11 ) 24 sequences, respectively. table 4-27 , table 4-28 , table 4-29 , and table 4-30 show the audio sample distributions for each of the four audio groups. each distribution has 625 lines with 1920 samples. table 4-27: group 1 audio sample distribution [3] (1-1) ([4],[3] 11 ) 25 [4],[3] (12-1) [0],[3] (1-1) ([4],[3] 11 ) 24 [4],[3] (23-1) ,[0] samples 0 925 37 0 888 70 lines 0 300 12 1 288 24 table 4-28: group 2 audio sample distribution [3] (2-1) ([4],[3] 11 ) 25 [4],[3] (12-2) [0],[3] (2-1) ([4],[3] 11 ) 24 [4],[3] (23-2) ,[0] samples 3 925 34 3 888 67 lines 1 300 11 2 288 23 table 4-29: group 3 audio sample distribution [3] (3-1) ([4],[3] 11 ) 25 [4],[3] (12-3) [0],[3] (3-1) ([4],[3] 11 ) 24 [4],[3] (23-3) ,[0] samples 6 925 31 6 888 64 lines 2 300 10 3 288 22 table 4-30: group 4 audio sample distribution [3] (4-1) ([4],[3] 11 ) 25 [4],[3] (12-4) [0],[3] (4-1) ([4],[3] 11 ) 24 [4],[3] (23-4) ,[0] samples 9 925 28 9 888 61 lines 3 300 9 4 288 21
gs1582 data sheet 40117 - 1 november 2007 62 of 114 4.7.22.3 synchronous audi o sample distributions table 4-31 lists the audio sample distributions for synchronous audio at all the video frame rates supported by the gs1582. 4.7.23 audio mute when the audio_muten bits of the host interface are set high, the embedded audio sample data will be set to all zeros (null audi o packets). to set all the embedded audio channels to mute, set th e host interface audio_all bit high. refer to section 4.13.3 for gs1582 status and configuration registers. 4.8 ancillary data insertion horizontal or vertical ancillary data word s may be inserted on up to four different lines per video frame. in order to insert hanc data, the anc_type bit in the host interface, must be set low. vanc data ca n be inserted by setting the anc_type bit in the host interface high. by defaul t, at power up, hanc data insertion is selected. the user must write the ancillary data word s to be inserted, the line number for the insertion, and the total number of words to be inserted to the designated registers in the host interface. at power up, or after system reset, all anc data insertion line numbers and total number of words default to zero. all data words including the ancillary pa cket adf, dbn, dc, did, sdid, and checksum (placeholder) must be provided. the user provided checksum word is a placeholder. the correc t value will be calculated and inserted automatically. two modes of operation are provided ? separate line mode and concatenated mode. by default, at power up or after sy stem reset, separate line operating mode is selected. the gs1582 ancillary data inse rtion provides no error c hecking or correction. the provided ancillary da ta must be fully smpte compliant. table 4-31: synchronous audio sample distributions frame rate (fps) samples per video frame 30 1600/1 29.97 8008/5 25 1920/1 60 800/1 59.94 4004/5 24 2000/1 23.98 2002/1
gs1582 data sheet 40117 - 1 november 2007 63 of 114 the packet_missed bit in the host interface is set if: ? an ancillary data packet is only partia lly inserted because there is no more free space in the hanc or vanc region of the selected line ? an ancillary data packet is not inserted at all because there is no free space in the hanc or vanc region of the selected line ? the number of words to insert programmed through the host interface is greater than the maximum allowed for the operating mode (128 in separate line mode or 512 in concat enated line mode). under th is condition, the bit will be set once the maximum number has been reached this bit is cleared once per frame on the risi ng edge of v or when it is read through the host interface. in sd mode, two modes of operation are provided ? separate line mode and concatenated mode. by default, at power up or after system reset, separate line operating mode is selected. ancillary data packets are inserted into the multiplexe d ycbcr video stream. in hd mode, by default ancillary data packets will be inserted into the luma channel. insertion in the chroma chann el may be selected via th e host interface. ancillary data insertion in the luma and chroma channels can be selected on a per line basis. ancillary data insertion only ta kes place if the ioproc_en/dis pin is set high, smpte_bypass is set high, and the anc_ins bit in the ioproc_disable register is set low. note 1: it is good practice to progr am the ancillary da ta words prior to programming the line nu mber and number of words. ancillary da ta insertion only begins once the line number and number of words are set to a non-zero value. therefore, this practice ensur es that no data is written to the anc space before the programming is complete. as such, no un intended data is written to the anc space, even if the programmed line number is reached before the programming is complete. also, read/write conflicts are avoided. note 2: in both separate line mode and concatenated mode, more than one anc packet may be inserted per line. the us er provided anc packets must contain a checksum place holder word. the correct checksu m for each packet will then be re-calculated and inserted by gs1582. the total number of words for all the provided ancillary data packets with chec ksum should not exceed 128 in separate line mode and 512 in concatenated mode. 4.8.1 ancillary data insertion operating mode 4.8.1.1 separate line mode in separate line mode, it is possible to insert horizontal or vertical ancillary data on up to four lines per video frame. for each of the four video lines, up to 128 8-bit hanc or vanc data words can be inserted. separate line mode is selected by setting the anc_ins_mode bit in the host interface low. by default, at power up, separate line mode is selected.
gs1582 data sheet 40117 - 1 november 2007 64 of 114 the non-zero video line numbers on which to insert th e ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert per line must be provided via the host interf ace. at power up, or after system reset, all ancillary data insertion line numbers and total number of words default to zero. if the total number of data words specified per line exceeds 128 only the first 128 data words will be inserted. the device automatically converts the pr ovided 8-bit data words into the 10-bit data, formatted acco rding to smpte 291m prior to insertion. 4.8.1.2 concatenated mode in concatenated mode, it is possible to in sert up to 512 8-bit horizontal or vertical ancillary data words on one line per vide o frame. concatenate d line mode can be selected by setting the anc_ins_mode bit in the host interface high. by default, at power up, separate line mode is selected. the non-zero video line number on which to insert the ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert must be provided via the host interfac e. at power up, or after s ystem reset, the ancillary data insertion line number and total number of words default to zero. if the total number of data words specified exceeds 512 only the first 512 data words will be inserted. the device automatically converts the provi ded 8-bit data words into the 10-bit data formatted according to smpte 291m prior to insertion. 4.8.2 hanc insertion by default, at power up or after system rese t, all ancillary data is inserted in the hanc space. data is insert ed contiguously starting at the trs eav or the first available location following any audio and pre-existing ancillary data packets. data insertion terminates when all provided data words have been inserted or at the start of the trs sav code, whichever occurs first. if terminatio n occurs before all words have been inserted, the packet_missed bi t will be set in the host interface. note 1: edh packet insertion in sd mode occurs following ancillary data insertion. thus, any hanc data inserted on the same line as the edh packet may be overwritten during edh insertion. when hanc data is inserted on an edh line, the packet_missed bit may be erroneously set, even though th e ancillary data packet has been inserted correctly. note 2: hanc space ancilla ry data headers un dergo 8-bit to 10-bit remapping. this means that when the 8 msbs are all zero, the value gets mapped to 000 and when the 8 msbs are all 1, the value gets mapped to 3ff. (i.e. 000, 001, 002, 003 ??> 000 and 3fe, 3fd, 3fc ??> 3ff)
gs1582 data sheet 40117 - 1 november 2007 65 of 114 4.8.3 vanc insertion ancillary data insertion into the vanc space can be selected via the host in terface. data is inserted contiguously starting at the trs sav or the first available location following any pre-existing ancillary data packets. data insertion terminates when all provided data words have been inserted or at the start of the trs eav code, whichever occurs first. if te rmination occurs before all words have been inserted, the packet_missed bit will be set in the host interface. note: when ancillary data is inserted into the active region of the video raster using the vanc feature, if the il legal_remap in the ioproc_disable register bit is set to 0, then the adfs are remapped to '004 | 3fb | 3fb' and the downstream devices will not dete ct the ancillary data packets. 4.9 additional processing functions the gs1582 incorporates additional data processing which is available in smpte mode only, see smpte mode on page 28 . 4.9.1 anc data blanking the horizontal and vert ical ancillary spaces of the in put video may be 'blanked' by the gs1582. in this mode, the trs words and active video will be preserved. any additional processing functions including audio embedding, incl uding ancillary data insertion, occur after blanking and will be present in the ou tput video stream. this function is enabled by setting the anc_blank pin low. 4.9.2 automatic video standard detection the gs1582 can detect the input video standard by using the timing parameters extracted from the received trs id word s, the supplied h_blanking, v_blanking, and f_digital timing signals, or the cea 861 timing signals, see hvf timing on page 28 and cea 861 timing on page 29 . this information is presented in the video_standard register ( table 4-32 ). total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and available via the raster_structure registers ( table 4-33 ). these line and sample count registers are updated once per frame at the end of line 12. after device reset, the four raster_s tructure registers default to zero.
gs1582 data sheet 40117 - 1 november 2007 66 of 114 4.9.3 video standard indication the value reported in the vd_std[4:0] bits of the video_standard register corresponds to the smpte standards as shown in table 4-34 . in addition to the 5-bit video standard code word, the video_standard register also contains two status bits. the std_ lock bit will be set high whenever the device has achieved full synchronization. the int_prog bit will be set low if the detected video standard is progressive and high if the detected video standard is interlaced. the vd_std[4:0], std_lock and int_prog bits of the video_standard register will default to zero after devi ce reset. the vd_std[4:0] and int_prog bits will also default to zero if the smpte_bypass pin is asserted low. the std_lock bit will retain its previous value if the pclk is removed. table 4-32: host interface descript ion for video standard register register name bit name description r/w default video_standard address: 004h 15 ? not used. ? ? 14-10 vd_std[4:0] video data standard (see table 4-34 ). r 0 9int_prog interlace/progressive: set low if detected video standard is progressive and is set high if it is interlaced. r0 8 std_lock standard lock: set high when the device has achieved full synchronization. r0 7-0 ? not used. ? ? table 4-33: host interface descript ion for raster structure registers register name bit name description r/w default raster_structure1 address: 00eh 15-12 ? not used. ? ? 11-0 raster_structure_1[11:0] words per active line r 0 raster_structure2 address: 00fh 15-13 ? not used. ? ? 12-0 raster_structure_2[12:0] words per total line. r 0 raster_structure3 address: 010h 15-11 ? not used. ? ? 10-0 raster_structure_3[10:0] total lines per frame r 0 raster_structure4 address: 011h 15-11 ? not used. ? ? 10-0 raster_structure_4[10:0] active lines per field r 0
gs1582 data sheet 40117 - 1 november 2007 67 of 114 table 4-34: supported video standards vd_std[4:0] smpte standard video format length of hanc length of active video total samples smpte352m lines 00h 296m (hd) 1280x720/60 (1:1) 358 1280 1650 13 01h 296m (hd) 1280x720/60 (1:1) - em 198 1440 1650 13 02h 296m (hd) 1280x720/30 (1:1) 2008 1280 3300 13 03h 296m (hd) 1280x720/30 (1:1) - em 408 2880 3300 13 04h 296m (hd) 1280x720/50 (1:1) 688 1280 1980 13 05h 296m (hd) 1280x720/50 (1:1) - em 240 1728 1980 13 06h 296m (hd) 1280x720/25 (1:1) 2668 1280 3960 13 07h 296m (hd) 1280x720/25 (1:1) - em 492 3456 3960 13 08h 296m (hd) 1280x720/24 (1:1) 2833 1280 4125 13 09h 296m (hd) 1280x720/24 (1:1) - em 513 3600 4125 13 0ah 274m (hd) 1920x1080/60 (2:1) or 1920x1080/30 (psf) 268 1920 2200 10, 572 0bh 274m (hd) 1920x1080/30 (1:1) 268 1920 2200 18 0ch 274m (hd) 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 1920 2640 10, 572 0dh 274m (hd) 1920x1080/25 (1:1) 708 1920 2640 18 0eh 274m (hd) 1920x1080/25 (1:1) - em 324 2304 2640 18 0fh 274m (hd) 1920x1080/25 (psf) - em 324 2304 2640 10, 572 10h 274m (hd) 1920x1080/24 (1:1) 818 1920 2750 18 11h 274m (hd) 1920x1080/24 (psf) 818 1920 2750 10, 572 12h 274m (hd) 1920x1080/24 (1:1) - em 338 2400 2750 18 13h 274m (hd) 1920x1080/24 (psf) - em 338 2400 2750 10, 572 14h 295m (hd) 1920x1080/50 (2:1) 444 1920 2376 10, 572 15h 260m (hd) 1920x1035/60 (2:1) 268 1920 2200 10, 572 16h 125m (sd) 1440x487/60 (2:1) (or dual link progressive) 268 1440 1716 13, 276 17h 125m (sd) 1440x507/60 (2:1) 268 1440 1716 13, 276 19h 125m (sd) 525-line 487 generic ? ? 1716 13, 276 1bh 125m (sd) 525-line 507 generic ? ? 1716 13, 276 18h itu-r bt.656 (sd) 1440x576/50 (2:1) (or dual link progressive) 280 1440 1728 9, 322
gs1582 data sheet 40117 - 1 november 2007 68 of 114 4.9.4 packet generati on and insertion the gs1582 can also calculate, assemble and insert trs id words, and various types of ancillary data packets. these features are only availa ble when the ioproc_en/dis pin is set high. individual insertion features may be enabled or disabled via the ioproc_disable register ( table 4-35 ). all of the ioproc_disable register bits de fault to '0' after device reset, enabling all of the processing features. to disable any individual error correction feature, set the corresponding bit high in this register. 1ah itu-r bt.656 (sd) 625-line generic (em) ? ? 1728 9, 322 1dh unknown hd ? ? ? ? ? 1eh unknown sd ? ? ? ? ? 1ch, 1fh reserved ? ? ? ? ? note: though the gs1582 will work correctly on and serialize both 59.94hz and 60hz formats, it will not distinguish between the m. table 4-34: supported video standards (continued) vd_std[4:0] smpte standard video format length of hanc length of active video total samples smpte352m lines
gs1582 data sheet 40117 - 1 november 2007 69 of 114 4.9.4.1 smpte 352m payload id entifier packet insertion the gs1582 can generate and insert smpte 352m payl oad identifier ancillary data packets. when this feature is enabl ed, the device will automatica lly generate the ancillary data preambles, (did, sdid, dbn, dc), and calculate the checksum. the smpte table 4-35: host interface description fo r internal processing disable register register name bit name description r/w default ioproc_disable address: 000h 15-13 ? not used. set to zero. ? 0 12 tim_861_pin_en setting this bit low allows the timing mode to be selectable through the cea_861bit. setting this bit high allows the timing mode to be selectable through the cea_861 bit, regardless of the pin setting. r/w 0 11 anc_ins enable or disable ancill ary data insertion. set low for enable. set high for disable. r/w 0 10 audio_embed disable audio embedding. r/w 0 9 cea_861 cea_861 pin override bit. active when tim_861_pin_en bit is set high. set cea_861 bit low to enable cea 861 timing. set this bit high to disable cea 861 timing. r/w 0 8 h_config horizontal blanking ti ming configuration. set low when the h/hsync input timing is based on active line blanking (default). set high when the h input timing is based on the h bit of the trs words. see figure 4-2 . r/w 0 7 ? not used. set to zero. ? 0 6 352m_ins smpte352m packet insertion. in hd mode, 352m packets are inserted in the luma channel only when one of the bytes in the video_format_a or video_format_b registers are programmed with non-zero values. set high to disable. r/w 0 5 illegal_remap illegal code rem apping. detection and correction of illegal code words within the active picture area (ap). set high to disable. r/w 0 4 edh_crc_ins error detection & handling (edh) cyclical redundancy check (crc) error correction. in sd mode the gs1582 will generate and insert edh packets. set high to disable. r/w 0 3 anc_csum_ins ancillary data checksum insertion. set high to disable. r/w 0 2 crc_ins luma and chroma line-based crc insertion. in hd mode, line-based crc words are inserted in both the luma and chroma channels. set high to disable r/w 0 1 lnum_ins luma and chroma line number insertion - hd mode only. set high to disable. r/w 0 0 trs_ins timing reference signal insertion. set high to disable. r/w 0
gs1582 data sheet 40117 - 1 november 2007 70 of 114 352m packet will be inserted into the dat a stream according to the line numbers programmed in the line_352m_f1 and line_352m_f2 registers ( table 4-36 ). packet insertion will only take place if at least one of the bytes in the video_format_a or video_format_b registers are programmed with a non-zero value ( table 4-37 ). in addition, the 352m_ins bit must be set low ( table 4-35 ). note: if there are existing 352m packets in the input stream, and anc_blank is set high (disabled), then the existing data is preserved and new 352m is inserted. the gs1582 does not overwrite existing 352m data. the gs1582 will differentiate between psf and interlaced formats based on bits 14 and 15 of the video_format_a register. the packets will be inse rted immediately after the eav word in sd video streams and immediately after the line-based crc word in the luma channel of hd video streams. if other ancillary packets exist in the horizontal ancillary space 352m packets will be inserted imme diatly following these pack ets. smpte 352m packets will not be inserted if th ere is insufficient room in the hanc space. table 4-36: host interface description for smpte 352m packet line number insertion registers register name bit name description r/w default line_0_352m address: 01bh 15-11 ? not used. ? ? 10-0 line_0_352m[10:0] line number where smpte352m packet is inserted in field 1. r/w 0 line_1_352m address: 01ch 15-11 ? not used. ? ? 10-0 line_1_352m[10:0] line number where smpte352m packet is inserted in field 2. r/w 0 table 4-37: host interface description for smpte 352m payload id entifier registers register name bit name description r/w default video_format_b address: 00bh 15-8 video_format[2] [7:0] smpte352m byte 4 information must be programmed in this register when 352m_ins = low. r/w 0 7-0 video_format[1] [7:0] smpte352m byte 3information must be programmed in this register when 352m_ins = low. r/w 0 video_format_a address: 00ah 15-8 video_format[4] [7:0] smpte352m byte 2information must be programmed in this register when 352m_ins = low. r/w 0 7-0 video_format[3] [7:0] smpte352m byte 1information must be programmed in this register when 352m_ins = low. r/w 0
gs1582 data sheet 40117 - 1 november 2007 71 of 114 4.9.4.2 illegal code remapping if the illegal_remap bit of the iopr oc_disable register is set low, the gs1582 will remap all codes within the acti ve picture between the values of 3fch and 3ffh to 3fbh. all codes within the ac tive picture area between the values of 000h and 003h will be remapped to 004h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values. 4.9.4.3 edh generation and insertion when operating in sd mode, (sd/hd = high), the gs1582 will generate and insert complete edh packets. packet gener ation and insertion will only take place if the edh_crc_ins bit of the iopr oc_disable register is set low. the gs1582 will g enerate all of t he required edh packet data including all ancillary data preambles did, dbn, dc, rese rved code words, and the checksum. calculation of both full field (ff) and active picture ( ap) crc's will be carried out by the device. smpte rp165 specifies the calculation ranges and scope of edh data for standard 525 and 625 component digita l interfaces. the gs1582 uses these standard ranges by default. if the received video format does not correspond to 525 or 625 digital component video standards, then the ranges will be determined from the received trs id words or supplied h_blanking, v_blanking, and f_digital timing signals; or hsync, vsync and de cea 861 timing signals. see hvf timing on page 28 , and cea 861 timing on page 29 . the first active and full field pixel will al ways be the first pixel after the sav trs code word. the last active and full field pi xel will always be the last pixel before the start of the eav trs code words. edh error flags (edh, eda, idh, ida and ues) for ancillary data, full field and active picture will also be inserted when the correspon ding bit of the edh_flag register is set high. ( table 4-38 ). note 1: the edh flag registers must be updated once per field. the prepared edh packet will be inserted at the approp riate line according to smpte rp165. the start pixel position of the inserted packet will be based on the sav position of that line such th at the last byte of the edh pack et (the checksum) will be placed in the sample immediatel y preceding the start of the sav trs word. note 2: edh packets will not be inserted if there is insu fficient room in the hanc space.
gs1582 data sheet 40117 - 1 november 2007 72 of 114 table 4-38: host interface description fo r edh flag register (sd mode only) register name bit name description r/w default edh_flag address: 002h 15 ? not used. ? ? 14 anc-ues ancillary unknown error status flag will be generated and inserted. r/w 0 13 anc-ida ancillary internal device error detected already flag will be generated and inserted. r/w 0 12 anc-idh ancillary internal device error detected here flag will be generated and inserted. r/w 0 11 anc-eda ancillary error de tected already flag will be generated and inserted. r/w 0 10 anc-edh ancillary error detected here flag will be generated and inserted. r/w 0 9 ff-ues full field unknown error flag will be generated and inserted. r/w 0 8 ff-ida full field internal device error detected already flag will be generated and inserted. r/w 0 7 ff-idh full field internal device error detected flag will be generated and inserted. r/w 0 6 ff-eda full field error detected already flag will be generated and inserted. r/w 0 5 ff-edh full field error detected here flag will be generated and inserted. r/w 0 4 ap-ues active picture unknown error status flag will be generated and inserted. r/w 0 3 ap-ida active picture internal device error detected already flag will be generated and inserted. r/w 0 2 ap-idh active picture internal device error detected here flag will be generated and inserted. r/w 0 1 ap-eda active picture error detected already flag will be generated and inserted. r/w 0 0 ap-edh active picture error detected here flag will be generated and inserted. r/w 0
gs1582 data sheet 40117 - 1 november 2007 73 of 114 4.9.4.4 ancillary data checks um generation and insertion the gs1582 will calculate ch ecksums for all detected ancillary data packets presented to the device. these calculated checksum values are inserted into the data stream prior to serialization. ancillary data checksum generation and insertion will only take place if the anc_csum_ins bit of the iopro c_disable register is set low. note: the gs1582 will recalculate the che cksum and, if incorrect, will re-insert the correct value. however, the gs1582 does not check the correctness of the parity bit. that is, if all the bits from 0 to 8 in the checksum word are correct and only bit 9 (the parity bit, which is the invers e of bit 8) is incorrect, then the checksum word is not re-calculated. if even one of bit 0 to bit 8 has an incorrect value, then the checksum word is re-calculated and re-inserted. 4.9.4.5 line based crc ge neration and insertion the gs1582 will gene rate and insert line based crc words into both the luma and chroma channels of the data stream. this feature is only available in hd mode and is enabled by setting the crc_ins bit of the ioproc_disable register low. 4.9.4.6 hd line number generation and insertion in hd mode, the gs1582 will calculate and insert line nu mbers into the luma and chroma channels of the output data stream. line number generation is in accordance with the relevant hd video standard as determined by the device, see automatic video standard detection on page 65 . this feature is enabled when sd/hd = low, and the lnum_ins bit of the ioproc_disable register is set low. 4.9.4.7 trs generation and insertion the gs1582 can generate and insert 10-bit trs code words into the data stream as required. this feature is enabled by setting the trs_ins bit of the ioproc_disable register low. trs word generation will be performed in accord ance with the timing parameters generated by the devi ce which will be locked either to the received trs id words, the supplied h_blanking, v_blanking, and f_ digital timing signals, or the cea 861 timing signals, see hvf timing on page 28 and cea 861 timing on page 29 . 4.10 parallel to serial conversion the gs1582 can accept either 10-bit or 20-bit parallel data in both sd and hd modes. the supplied pclk rate must corr espond to the settings of the sd/hd and 20bit/10bit pins as shown in table 4-39 .
gs1582 data sheet 40117 - 1 november 2007 74 of 114 4.11 internal clockcleaner tm pll to obtain a clean clock signal for serialization and transmission, an external vco signal is locked to the input pclk via th e gs1582's integrated phase-locked loop. this high quality analog pll has a bang-bang implementation, which automatically narrows the loop bandwidth in the presence of jitter, allowing the gs1582 to significantly attenuate jitter on the incoming pclk. 4.11.1 external vco the gs1582 requir es the go1555 external voltage controlled oscillator as part of its internal pll. power for the external vco is generated by the gs1582 from an integrated voltage regulator. the internal regulator uses +3.3v supplied on the cp_vdd / cp_gnd pins to provide +2.5v on the vco_vcc / vco_gnd pins. the external vco produces a 1.485ghz si gnal for the pll, input on the vco pin of the device. see typical application circu it (part a) on page 108 . note: the vco_vcc output voltage is guaranteed to be 2.5v only when supplying power to the go1555. the vco_ vcc pin should not be shorted to gnd under any circumstances. 4.11.2 loop filter the gs1582 pll loop filter is an external first order filter formed by a series rc connection as shown in the typical application circuit (part a) on page 108 . the loop filter resistor value sets the band width of the pll and the capacitor value controls its stability and lock time. a l oop filter resistor value between 1 to 20 and a loop filter capacitor value between 1f to 33f are recommended. the gs1582 uses a non-linear, bang-bang, pll, therefore its bandwidth scales with the input jitter amplitude - greater input jitter results in a sm aller loop bandwidth causing more of the input jitte r to be rejected. for a given input jitter amplitude, a smaller loop filter resistor produces a nar rower loop bandwidth. with an input jitter amplitude of 300ps, for example, the pll bandwidth can be adjusted from 2khz to table 4-39: serial digital output rates supplied pclk rate serial digital output rate pin settings sd/hd 20bit/10bit 74.25 or 74.25/1.001 mhz 1.485 or 1.485/1.001gb/s low high 148.5 or 148.5/1.001mhz 1.485 or 1.485/1.001gb/s low low 13.5mhz 270mb/s high high 27mhz 270mb/s high low
gs1582 data sheet 40117 - 1 november 2007 75 of 114 40khz by varying the loop f ilter resistor, as shown in table 4-40: loop filter component values . for use with the gen-clocks tm timing generators, a narrow loop bandwidth is recommended. increasing the loop filter capacitor value incr eases the stability of the pll, but results in a longer lock time. for loop filter resistors smaller than 7 , a capacitor value of 33f is recommended, while larger resistor values can accommodate smaller capacitors. sample co mbinations of the loop filt er resistor and capacitor values are shown in table 4-40: loop filter component values , along with the resulting loop bandwidth. additional loop bandwidths can be achieved by using different loop filter resistor values. 4.11.3 lock detect output the locked output will be a sserted high when the in ternal pll has locked to the input pclk signal. in the absence of the pclk, when frequency lock has not been achieved, an d during device reset, the locked output will be low. lock time, the time it takes for the intern al pll to frequency- lock to the reference pclk following power-up or standby, is determined by the loop filter capacitor value chosen. a 1 f loop filter capacitor, for exam ple, will result in lock times of less than 500 s. a 33 f loop filter capacitor, on th e other hand, will result in a lock time of greater than 5s. note 1: when the pll is in the proces s of locking to the reference pclk, the locked pin may generate low and high pulses. the durations of these pulses are dependent on the loop filter capacitor value, but do not exceed 30ms. once the pll has achieved frequency lock, the locked pin will remain high and not change state. note 2: when the gs1582 is placed in standby mode, the value of locked is maintained although the pll does lose lock to the reference pclk. when standby is released, the pll will re-lock. during this time, if the locked pin was previously high, it will de-assert approximately 6 s later, and re-assert once the pll has re-locked to the input pclk. table 4-40: loop filter component values loop filter resistor value typical loop bandwidth* recommended loop filter capacitor value comments 1 2khz 33 f narrow bandwidth - provides maximum jitter reduction. long lock-time. 7 8khz 10 f 20 40khz 1 f wide bandwidth. fast lock-time. * measured with 300ps pk-pk input jitter on pclk
gs1582 data sheet 40117 - 1 november 2007 76 of 114 4.12 serial digital output the gs1582 includes a smpte compliant current mode differential serial digital cable driver with automatic slew rate control. the serial output has improved eye quality, exceptional orl performance, and reduced duty cycle distortion. the cable driver uses a separate +3.3 v dc power supply provided via the cd_vdd and cd_gnd pins. to enable the output, sdo_en/dis must be set high. setting the sdo_en/dis signal low will set the sdo and sdo output pins to high impedance, resulting in reduced device power consumption. 4.12.1 output swing nominally, the voltage swing of the serial digital output is 800mvp-p single-ended into a 75 load. this is set exte rnally by connecting the rset pin to cd_vdd through 750 1% resistor . 4.13 gspi host interface the gs1582 host interface, also called the gennum serial peripheral interface (gspi), provides access to configuration/ status registers for the video processing and sd and hd audio processing functions of the chip. by default, the device will be ?live at po wer up? with all major functional blocks active in the defined default oper ating conditions described below. dedicated configuration pins are provided for basic configuration of the device. the host interface is provided to allow opt ional configuration of some of the more advanced functions and operating modes of the device. to simplify host interface access to the configuration and status registers, a single contiguous register map is provided for the video and audio functions. registers are grouped by like function and wherever possible functional configuration will not be spread across multiple registers. the gspi is comprised of a serial data inpu t signal (sdin), serial data output signal (sdout), an active low chip select (cs ), and a burst clock (sclk). the burst clock must have a duty cycle between 40% and 60% while active. because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs are inputs to the device. the sdout loops the sdin back out when gspi is in write mode, or when cs is high, allowing multiple devices to be co nnected in series. during reset, sdout is held in high-impedance mode. the interface is illustrated in the figure 4-26 .
gs1582 data sheet 40117 - 1 november 2007 77 of 114 each gspi access begins with a 16-bi t command word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. note 1: when operating in sd mode, sd/hd is set high, only the sd video and audio registers are accessible for read or write. similarly, when operating in hd mode, sd/hd is set low, only the hd video and audio registers are accessible for read or write. note 2: when the device is in stand by mode (standby = high) no host interface register can be read back or written to . attempting a read or write will not damage the device. however, all reads will re turn a value of 0, and no writes will take effect. note 3: in the configuration and status re gisters, there are several registers that have been designated as reserved. if poss ible, writing to these registers should be avoided. if writing a value to these regi sters is not avoidable, then only a value of 0 should be written to these registers. writing a value of 1 may alter the functional behaviour of gs1582 but will not permanently damage the device. figure 4-26: gennum serial peripheral interface (gspi) application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 gs1582 gs1582 cs
gs1582 data sheet 40117 - 1 november 2007 78 of 114 4.13.1 command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-increment bit and a 12-bit address. figure 4-27 shows the command word format and bit configurations. command words are clocked into the gs1582 on the rising edge of the serial clock sclk, which operates in a burst fashion. when the auto-increment bit is set lo w, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word will be wri tten into the address specified in the command word, and subseq uent data words will be wri tten into incremental addresses from the previous data word. this facilitates multiple address writes without sending a command word for each data word. note: all registers can be written to through single address access or through the auto-increment feature. however, the lsb of the video registers cannot be read through single address read- back. single address read -back will return a 0 value for the lsb. if auto-increme nt is used to read back the values from at least two registers, the lsb value read will always be correct. therefore, for register read-back, it is recommende d that auto-increment be used and that at least two registers be read back at a time. figure 4-27: command word figure 4-28: data word 4.13.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 4-29 and figure 4-30 respectively. the timing parameters are defined in table 4-41 . when several devices are connected to the gspi chain, only one cs must be set low during a read sequence. during the write sequence, all command and subsequent data words are looped through from sdin to sdout. when seve ral devices are connected to the gspi chain, data can be written simultaneo usly to all the devices that have cs set low. msb lsb a4 a5 a6 a8 a7 a9 a3 a2 a1 a0 a10 a11 autoinc rsv rsv r/w rsv = reserved. must be set to zero. r/w: read command when r/w = 1 write command when r/w = 0 msb lsb d4 d5 d6 d8 d7 d9 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15
gs1582 data sheet 40117 - 1 november 2007 79 of 114 figure 4-29: gspi read mode timing figure 4-30: gspi write mode timing table 4-41: gspi timing parameters parameter definition specification t 0 the minimum duration of time chip select, cs , must be low before the first sclk rising edge. 1.5 ns t 1 the minimum sclk period. 100 ns t 2 duty cycle tolerated by sclk. 40% to 60% t 3 minimum input setup time. 1.5 ns t 4 write cycle: the minimum duration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 37.1 ns t 5 read cycle: the minimum duration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 148.4 ns t 6 minimum output hold time. 1.5 ns t 7 the minimum duration of time between the last sclk of the gspi transaction and when cs can be set high. 37.1 ns t 8 minimum input hold time. 1.5 ns sclk cs sdin sdout t 5 t 6 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 3 sclk cs sdin sdout t 0 t 1 t 2 t 4 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 7 t 8
gs1582 data sheet 40117 - 1 november 2007 80 of 114 4.13.3 configuration and status registers table 4-42 summarizes the gs1582's internal st atus and configuration registers. table 4-43 summarizes the video status and configuration registers. table 4-44 and table 4-45 summarizes the sd and hd audio status and configuration registers. all bits are available to the host via the gspi. table 4-42: gs1582 internal registers address register name see section 000h ioproc_disable section 4.9.4 002h edh_flag section 4.9.4.3 004h video_standard section 4.9.2 005h - 009h anc_data_type 00ah - 00bh video_format section 4.9.4.1 00eh - 011h raster_structure section 4.9.2 01ah global_error_mask_vector 01bh - 01ch line_352m section 4.9.4.1
gs1582 data sheet 40117 - 1 november 2007 81 of 114 4.13.3.1 video registers table 4-43: video configuration and status registers address register name bit description r/w default 000h reserved 15-13 reserved. r 000b tim_861_pin_en 12 selects pin for control for 861 timing converter. reference: section 4.3.2 on page 29 . r/w 0 anc_ins 11 disable for ancillary data insertion feature. reference: section 4.8 on page 62 . r/w 0 audio_embed 10 disable audio embedding. reference: section 4.7 on page 36 . r/w 0 cea_861 9 disable 861 timing converter. reference: section 4.3.2 on page 29 . r/w 0 h_config 8 horizontal sync timing i nput configuration. set low when the h input timing is bas ed on active line blanking (default). set high when the h input timing is based on the h bit of the trs words. reference: section 4.3.1 on page 28 . r/w 0 reserved 7 reserved. r 0 352m_ins 6 smpte352m packet insertion. in hd mode, 352m packets are inserted in the luma channel only when one of the bytes in the video_format_a or video_format_b registers are programmed with non-zero values. set high to disable. reference: section 4.9.4.1 on page 69 . r/w 0 illegal_remap 5 illegal code remapping. detection and correction of illegal code words within the active picture area (ap). set high to disable. reference: section 4.9.4.2 on page 71 . r/w 0 edh_crc_ins 4 error detection & handling (edh) cyclical redundancy check (crc) error correction. in sd mode the gs1582 will generate and insert edh packets. set high to disable. reference: section 4.9.4.3 on page 71 . r/w 0 anc_csum_ins 3 ancillary data checksu m insertion. set high to disable. reference: section 4.9.4.4 on page 73 . r/w 0 crc_ins 2 luma and chroma line-based crc insertion. in hd mode, line-based crc words are inserted in both the luma and chroma channels. set high to disable reference: section 4.9.4.5 on page 73 . r/w 0 lnum_ins 1 luma and chroma line number insertion - hd mode only. set high to disable. reference: section 4.9.4.6 on page 73 . r/w 0 trs_ins 0 timing reference signal insertion. set high to disable. reference: section 4.9.4.7 on page 73. r/w 0
gs1582 data sheet 40117 - 1 november 2007 82 of 114 001h reserved 15-0 reserved. r n/a 002h reserved 15 reserved. r/w 0 anc-ues 14 ancillary unknown erro r status flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 anc-ida 13 ancillary internal devic e error detected already flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w anc-idh 12 ancillary internal devic e error detected here flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 anc-eda 11 ancillary error detect ed already flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 anc-edh 10 ancillary error detected here flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 ff-ues 9 full field unknown error flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 ff-ida 8 full field internal device error detected already flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 ff-idh 7 full field internal device error detected flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 ff-eda 6 full field error detect ed already flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 ff-edh 5 full field error detected here flag will be generated and inserted. sd mode only. reference: section 4.9.4.3 on page 71. r/w 0 ap-ues 4 active picture unknow n error status flag will be generated and inserted. sd mode only. r/w 0 ap-ida 3 active picture internal device error detected already flag will be generated and inserted. sd mode only. r/w 0 ap-idh 2 active picture internal devic e error detected here flag will be generated and inserted. sd mode only. r/w 0 ap-eda 1 active picture error detected already flag will be generated and inserted. sd mode only. r/w 0 ap-edh 0 active picture error detected here flag will be generated and inserted. sd mode only. r/w 0 003h reserved 15-0 reserved. r n/a table 4-43: video configuration an d status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 83 of 114 004h reserved 15 reserved r 0 vid_std[4:0] 14-10 reports the detected video standard. reference: section 4.9.3 on page 66 . r 00000b int_prog 9 interlace/progressive: set low if detected video standard is progressive and is set high if it is interlaced. reference: section 4.9.3 on page 66 . r0 std_lock 8 standard lock: set high when the device has achieved full synchronization. reference: section 4.9.3 on page 66 . r0 reserved 7-0 reserved. r n/a 005h-009h reserved 15-0 reserved. r n/a 00ah video_format_a[15:8] 15-8 smpte 352m byte 2 information must be programmed in this register when 352m_ins = low. reference: section 4.9.4.1 on page 69 . r/w 0 video_format_a[7:0] 7-0 smpte 352m byte 1 information must be programmed in this register when 352m_ins = low. reference: section 4.9.4.1 on page 69 . r/w 0 00bh video_format_b[15:8] 15-8 smpte 352m byte 4 information must be programmed in this register when 352m_ins = low. reference: section 4.9.4.1 on page 69 . r/w 0 video_format_b[7:0] 7-0 smpte 352m byte 3 information must be programmed in this register when 352m_ins = low. reference: section 4.9.4.1 on page 69 . r/w 0 00ch-00dh reserved 15-0 reserved. r n/a 00eh reserved 15-12 reserved. ? ? raster_structure_1 11-0 words per active line reference: section 4.9.2 on page 65 . r0 00fh reserved 15-13 reserved. ? ? raster_structure_2 12-0 words per total line. reference: section 4.9.2 on page 65 . r0 010h reserved 15-11 reserved. ? ? raster_structure_3 10-0 total lines per frame reference: section 4.9.2 on page 65 . r0 011h reserved 15-11 reserved. ? ? raster_structure_4 10-0 active lines per field reference: section 4.9.2 on page 65 . r0 table 4-43: video configuration an d status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 84 of 114 012h reserved 15-10 not used. set to zero. ? 0 ap_line_start_f0[9:0] 9-0 field 0 active picture start line data used to set edh calculation range outside of rp 165 values. r/w 0 013h reserved 15-10 reserved. ? ? ap_line_end_f0[9:0] 9-0 field 0 active picture end line data used to set edh calculation range outside of rp 165 values. r/w 0 014h reserved 15-10 reserved. ? ? ap_line_start_f1[9:0] 9-0 field 1 active picture start line data used to set edh calculation range outside of rp 165 values. r/w 0 015h reserved 15-10 reserved. ? ? ap_line_end_f1[9:0] 9-0 field 1 active picture end line data used to set edh calculation range outside of rp 165 values. r/w 0 016h reserved 15-10 reserved. ? ? ff_line_start_f0[9:0] 9-0 field 0 full field start line data used to set edh calculation range outside of rp 165 values. r/w 0 017h reserved 15-10 reserved. ? ? ff_line_end_f0[9:0] 9-0 field 0 full field end line data used to set edh calculation range outside of rp 165 values. r/w 0 018h reserved 15-10 reserved. ? ? ff_line_start_f1[9:0] 9-0 field 1 full field start line data used to set edh calculation range outside of rp-165 values. r/w 0 019h reserved 15-10 reserved. ? ? ff_line_end_f1[9:0] 9-0 field 1 full field end line data used to set edh calculation range outside of rp-165 values. r/w 0 01ah reserved 15-0 reserved. r n/a 01bh reserved 15-11 reserved. ? ? line_0_352m[10:0] 10-0 line number where smpte352m packet is inserted in field 1. reference: section 4.9.4.1 on page 69 . r/w 0 01ch reserved 15-11 reserved. ? ? line_1_352m[10:0] 10-0 line number where smpte352m packet is inserted in field 2. reference: section 4.9.4.1 on page 69 . r/w 0 01dh-01eh reserved 15-0 reserved. r n/a table 4-43: video configuration an d status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 85 of 114 01fh format_err 15 861 timing format error flag. r 0 reserved 14-9 reserved. r 0 line_offset 8-6 shifts the timing of the output 861 timing signal by up to +/-3 lines. r/w 0 pixel_offset 5-3 shifts the timing of the output 861 timing signal by up to +/-3 pixels. r/w 0 reserved 2-1 reserved. r 0 fsync_invert 0 inverts the polarity of the detected field. r/w 0 020h anc_ins_mode 15 selects the anc data insertion operating mode. 0 separate line mode 1 concatenated mode reference: section 4.8.1 on page 63 . r/w 0 packet_missed 14 flag to indicate ancillary data packet could not be inserted in its entirety. reference: section 4.8 on page 62 . r0 rw_conflict 13 flag to indicate the same ram address was read and written at the same time. r0 reserved 12-11 reserved r/w 0000b first_line_number 10-0 defines the line num ber for the first line in separate line mode or the single line for concatenated mode. r/w 0 021h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.8.2 & section 4.8.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.8.2 & section 4.8.3 r/w 0 reserved 13-10 reserved r/w 0000b first_line_number_of _words 9-0 defines the total number of data words to insert on the first line in separate line mode or single line in the concatenated mode. r/w 0 022h reserved 15-11 reserved r/w 00000b second_line_number 10-0 defines the line number for anc data insertion for the 2nd line in separate line mode. r/w 0 table 4-43: video configuration an d status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 86 of 114 023h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.8.2 & section 4.8.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.8.2 & section 4.8.3 r/w 0 reserved 13-10 reserved r/w 0000b second_line_number_ of_words 9-0 defines the total number of data words to insert on the 2nd line in separate line mode. r/w 0 024h reserved 15-11 reserved r/w 00000b third_line_number 10-0 defines the line number for anc data insertion for the 3rd line in separate line mode. r/w 0 025h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.8.2 & section 4.8.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.8.2 & section 4.8.3 r/w 0 reserved 13-10 reserved. r/w 0000b third_line_number_of _words 9-0 defines the total number of data words to insert on the 3rd line in separate line mode. r/w 0 026 reserved 15-11 reserved r/w 00000b fourth_line_number 10-0 defines the line num ber for anc data insertion for the 4th line in separate line mode. r/w 0 027h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.8.2 & section 4.8.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.8.2 & section 4.8.3 r/w 0 reserved 13-10 reserved r/w 0000b fourth_line_number_ of_words 9-0 defines the total number of data words to insert on the 4th line in separate line mode. r/w 0 table 4-43: video configuration an d status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 87 of 114 040h-07fh anc_data_bank1 15-0 first bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 080h-0bfh anc_data_bank2 15-0 second bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 0c0h-0ffh anc_data_bank3 15-0 third bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 100h-13fh anc_data_bank4 15-0 fourth bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 table 4-43: video configuration an d status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 88 of 114 4.13.3.2 sd audio registers table 4-44: sd audio configuration and status registers address register name bit description r/w default 400h ctr_agr 15 selects replacem ent of audio control packets. 0: do not replace audio control packets. 1: replace all audio control packets. reference: section 4.7.11 on page 48 . r/w 0 agr 14 selects audio group replacement operating mode. reference: section 4.7.11 on page 48 . r/w 0 one_agr 13 specifies the replacement of just the group 1 audio. 0: do not replace only group 1. 1: replace only group 1. reference: section 4.7.11 on page 48. r/w 0 ctrb_on 12 specifies the embedding of group 2 audio control packets. reference: section 4.7.9 on page 45 . r/w 1 clear_audio 11 clears all audio fifo buffers and puts them in start-up state reference: section 4.7.21 on page 58 . r/w 0 afnb_auto 10 group 2 audio frame number generation. reference: section 4.7.9 on page 45 . r/w 1 ctra_on 9 specifies the embedding of group 1 audio control packets. reference: section 4.7.9 on page 45 . r/w 1 24bit 8 specifies the sample size for embedded audio. reference: section 4.7.10 on page 47 . r/w 0 afna_auto 7 enables group 1 audio frame number generation. reference: section 4.7.9 on page 45 . r/w 1 afn_ofs[2:0] 6-4 offset to add to generated audio frame number. must be in the range of 0 to 4. the resulting audio frame number will wrap around so as to always be in the 1-5 range. reference: section 4.7.16 on page 51 . r/w 000b idb[1:0] 3-2 specifies the group 2 audio to embed. note: should ida and idb be set to the same value, they automatically revert to their default values. reference: section 4.7.10 on page 47 . r/w 01b (normal mode) 11b (cascade mode) ida[1:0] 1-0 specifies the group 1 audio to embed. note: should ida and idb be set to the same value, they automatically revert to their default values. reference: section 4.7.10 on page 47 . r/w 00b (normal mode) 10b (cascade mode)
gs1582 data sheet 40117 - 1 november 2007 89 of 114 401h reserved 15-11 reserved r 00000b aes_errd 10 stereo pair d audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 aes_errc 9 stereo pair c audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 aes_errb 8 stereo pair b audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 aes_erra 7 stereo pair a audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 reserved 6-3 reserved r 0 offset_disable 2 set to disable st aggering of group 2 audio sample distribution by one line. reference: section 4.7.20 on page 57 . r/w 0 os_sel[1:0] 1-0 specifies the audio fifo buffer size. 00: 52 samples deep, 26 sample start-up count 01: 24 samples deep, 12 sample start-up count 10: 12 samples deep, 6 sample start-up count 11: reserved. reference: section 4.7.21 on page 58 . r/w 00b table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 90 of 114 402h reserved 15 reserved. r 0 axpg4_det 14 set while group 4 audio extended packets are detected. reference: section 4.7.2 on page 37 . r0 axpg3_det 13 set while group 3 audio extended packets are detected. reference: section 4.7.2 on page 37 . r0 axpg2_det 12 set while group 2 audio extended packets are detected. reference: section 4.7.2 on page 37 . r0 axpg1_det 11 set while group 1 audio extended packets are detected. reference: section 4.7.2 on page 37 . r0 acpg4_det 10 set while group 4 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 acpg3_det 9 set while group 3 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 acpg2_det 8 set while group 2 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 acpg1_det 7 set while group 1 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 adpg4_det 6 set while group 4 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 adpg3_det 5 set while group 3 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 adpg2_det 4 set while group 2 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 adpg1_det 3 set while group 1 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 acs_apply_waitb 2 set while the multiplexer is waiting for a status boundary in the group b group before applying the acsr[183:0] data to that group. reference: section 4.7.18 on page 55 . r0 acs_apply / acs_apply_waita 1 acs_apply: cause channel satus data in acsr[183:0] to be transferred to the channel status replacement mechanism. the transfer shall not occur until the next status boundary. acs_apply_waita: set while the multiplexer is waiting for a status boundary in group 1 before applying the acsr[183:0] data. reference: section 4.7.18 on page 55 . r/w 0 acs_regen 0 specifies that audio channel status of all channels should be replaced with acsr[183:0] field. 0: do not replace channel status 1: replace channel status of all channels reference: section 4.7.18 on page 55 . r/w 0 table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 91 of 114 403h reserved 15-10 reserved. r n/a en_cascade 9 cascade. r/w reserved 8-0 reserved. r n/a 404h-407h reserved 15-0 reserved. r n/a 408h amd[1:0] 15-14 audio input format selector for stereo pair d input channels 7 and 8. reference: section 4.7.17 on page 52 . r/w 11b amc[1:0] 13-12 audio input format selector for stereo pair c input channels 5 and 6. reference: section 4.7.17 on page 52 . r/w 11b amb[1:0] 11-10 audio input format selector for stereo pair b input channels 3 and 4. reference: section 4.7.17 on page 52 . r/w 11b ama[1:0] 9-8 audio input format selector for stereo pair a input channels 1 and 2. reference: section 4.7.4 on page 39 . r/w 11b mute8 7 audio input channel 8 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute7 6 audio input channel 7 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute6 5 audio input channel 6 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute5 4 audio input channel 5 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute4 3 audio input channel 4 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute3 2 audio input channel 3 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute2 1 audio input channel 2 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute1 0 audio input channel 1 mute enable. reference: section 4.7.23 on page 62 . r/w 0 table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 92 of 114 409h reserved 15, 12 reserved r/w 0 gp1_wclk_src[2:0] 14-13 audio group 1 word clock source selector. reference: section 4.7.20 on page 57 . r/w 0 gp1_ch4_src[2:0] 11-9 audio group 1 channel 4 source selector. reference: section 4.7.19 on page 56 . r/w 011b gp1_ch3_src[2:0] 8-6 audio group 1 channel 3 source selector. reference: section 4.7.19 on page 56 . r/w 010b gp1_ch2_src[2:0] 5-3 audio group 1 channel 2 source selector. reference: section 4.7.19 on page 56 . r/w 001b gp1_ch1_src[2:0] 2-0 audio group 1 channel 1 source selector. reference: section 4.7.19 on page 56 . r/w 000b 40ah reserved 15, 12 reserved r/w 0 gp2_wclk_src[1:0] 14-13 audio group 2 word clock source selector. reference: section 4.7.20 on page 57 . r/w 10 gp2_ch4_src[1:0] 11-9 audio group 2 channel 4 source selector. reference: section 4.7.19 on page 56 . r/w 111b gp2_ch3_src[2:0] 8-6 audio group 2 channel 3 source selector. reference: section 4.7.19 on page 56 . r/w 110b gp2_ch2_src[2:0] 5-3 audio group 2 channel 2 source selector. reference: section 4.7.19 on page 56 . r/w 101b gp2_ch1_src[2:0] 2-0 audio group 2 channel 1 source selector. reference: section 4.7.19 on page 56 . r/w 100b table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 93 of 114 40bh en_not_locked 15 asserts audio_int when locked is not asserted. reference: section 4.7.14 on page 50 . r/w 0 en_no_video 14 asserts audio_int when the video format is unknown. reference: section 4.7.14 on page 50 . r/w 0 en_mux_errb 13 asserts audio_int when the mux_errb flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_mux_erra 12 asserts audio_int when the mux_erra flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_errd 11 asserts audio_int when the aes_errd flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_errc 10 asserts audio_int when the aes_errc flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_errb 9 asserts audio_int when the aes_errb flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_erra 8 asserts audio_int when the aes_erra flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg4_det 7 asserts audio_int when the acpg4_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg3_det 6 asserts audio_int when the acpg3_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg2_det 5 asserts audio_int when the acpg2_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg1_det 4 asserts audio_int when the acpg1_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg4_det 3 asserts audio_int when the adpg4_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg3_det 2 asserts audio_int when the adpg3_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg2_det 1 asserts audio_int when the adpg2_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg1_det 0 asserts audio_int when the adpg1_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 94 of 114 40ch mux_errb 15 set in cascade mode when the incoming video contains packets with the same group number as group 2. reference: section 4.7.3 on page 38 . r0 mux_erra 14 set in cascade mode when the incoming video contains packets with the same group number as group 1. reference: section 4.7.3 on page 38 . r0 xpoint_error 13 set when the crosspoint switch is configured to put the same audio channel in both group 1 and group 2. reference: section 4.7.19 on page 56 . r0 mute_all 12 mutes all input audio channels. reference: section 4.7.23 on page 62 . r/w 0 lsb_firstd 11 causes the fourth stereo pair serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 lsb_firstc 10 causes the third stereo pair serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 lsb_firstb 9 causes the second stereo pair serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 lsb_firsta 8 causes the first stereo pa ir serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 act8 7 specifies embedding of audio group 2 channel 4. reference: section 4.7.12 on page 50 . r/w 1 act7 6 specifies embedding of audio group 2 channel 3. reference: section 4.7.12 on page 50 . r/w 1 act6 5 specifies embedding of audio group 2 channel 2. reference: section 4.7.12 on page 50 . r/w 1 act5 4 specifies embedding of audio group 2 channel 1. reference: section 4.7.12 on page 50 . r/w 1 act4 3 specifies embedding of audio group 1 channel 4. reference: section 4.7.12 on page 50 . r/w 1 act3 2 specifies embedding of audio group 1 channel 3. reference: section 4.7.12 on page 50 . r/w 1 act2 1 specifies embedding of audio group 1 channel 2. reference: section 4.7.12 on page 50 . r/w 1 act1 0 specifies embedding of audio group 1 channel 1. reference: section 4.7.12 on page 50 . r/w 1 40dh-41fh reserved 15-0 reserved. w n/a table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 95 of 114 420h-436h reserved 15-8 reserved w n/a 420h acsr[7:0] 7-0 audio status block byte 0. reference: section 4.7.18 on page 55 . w 85h 421h acsr[15:8] 7-0 audio status block byte 1. reference: section 4.7.18 on page 55 . w 08h 422h acsr[23:16] 7-0 audio status block byte 2. reference: section 4.7.18 on page 55 . w2ch 423h-436h acsr[183:24] 7-0 remaining audio status. reference: section 4.7.18 on page 55 . w0 440h reserved 15-9 reserved w 0000000b del1a[7:0] 8-1 audio group 1 delay data for channel 1. reference: section 4.7.9 on page 45 . w0 ebit1a 0 audio group 1 delay data valid flag for channel 1. reference: section 4.7.9 on page 45 . w0 441h reserved 15-9 reserved w 0000000b del1a[16:8] 8-0 audio group 1 delay data for channel 1. reference: section 4.7.9 on page 45 . w0 442h reserved 15-9 reserved w 0000000b del1a[25:17] 8-0 audio group 1 delay data for channel 1. reference: section 4.7.9 on page 45 . w0 443h reserved 15-9 reserved w 0000000b del2a[7:0] 8-1 audio group 1 delay data for channel 2. reference: section 4.7.9 on page 45 . w0 ebit2a 0 audio group 1 delay data valid flag for channel 2. reference: section 4.7.9 on page 45 . w0 444h reserved 15-9 reserved w 0000000b del2a[16:8] 8-0 audio group 1 delay data for channel 2. reference: section 4.7.9 on page 45 . w0 445h reserved 15-9 reserved w 0000000b del2a[25:17] 8-0 audio group 1 delay data for channel 2. reference: section 4.7.9 on page 45 . w0 446h reserved 15-9 reserved w 0000000b del3a[7:0] 8-1 audio group 1 delay data for channel 3. reference: section 4.7.9 on page 45 . w0 ebit1a 0 audio group 1 delay data valid flag for channel3. reference: section 4.7.9 on page 45 . w0 table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 96 of 114 447h reserved 15-9 reserved w 0000000b del3a[16:8] 8-0 audio group 1 delay data for channel 3. reference: section 4.7.9 on page 45 . w0 448h reserved 15-9 reserved w 0000000b del3a[25:17] 8-0 audio group 1 delay data for channel 3. reference: section 4.7.9 on page 45 . w0 449h reserved 15-9 reserved w 0000000b del4a[7:0] 8-1 audio group 1 delay data for channel 4. reference: section 4.7.9 on page 45 . w0 ebit4a 0 audio group 1 delay data valid flag for channel 4. reference: section 4.7.9 on page 45 . w0 44ah reserved 15-9 reserved w 0000000b del4a[16:8] 8-0 audio group 1 delay data for channel 4. reference: section 4.7.9 on page 45 . w0 44bh reserved 15-9 reserved w 0000000b del4a[25:17] 8-0 audio group 1 delay data for channel 4. reference: section 4.7.9 on page 45 . w0 450h reserved 15-9 reserved w 0000000b del1b[7:0] 8-1 audio group 2 delay data for channel 1. reference: section 4.7.9 on page 45 . w0 ebit1b 0 audio group 2 delay data valid flag for channel 1. reference: section 4.7.9 on page 45 . w0 451h reserved 15-9 reserved w 0000000b del1b[16:8] 8-0 audio group 2 delay data for channel 1. reference: section 4.7.9 on page 45 . w0 452h reserved 15-9 reserved w 0000000b del1b[25:17] 8-0 audio group 2 delay data for channel 1. reference: section 4.7.9 on page 45 . w0 453h reserved 15-9 reserved w 0000000b del2b[7:0] 8-1 audio group 2 delay data for channel 2. reference: section 4.7.9 on page 45 . w0 ebit2b 0 audio group 2 delay data valid flag for channel 2. reference: section 4.7.9 on page 45 . w0 454h reserved 15-9 reserved w 0000000b del2b[16:8] 8-0 audio group 2 delay data for channel 2. reference: section 4.7.9 on page 45 . w0 table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 97 of 114 455h reserved 15-9 reserved w 0000000b del2b[25:17] 8-0 audio group 2 delay data for channel 2. reference: section 4.7.9 on page 45 . w0 456h reserved 15-9 reserved w 0000000b del3b[7:0] 8-1 audio group 2 delay data for channel 3. reference: section 4.7.9 on page 45 . w0 ebit1b 0 audio group 2 delay data valid flag for channel3. reference: section 4.7.9 on page 45 . w0 457h reserved 15-9 reserved w 0000000b del3b[16:8] 8-0 audio group 2 delay data for channel 3. reference: section 4.7.9 on page 45 . w0 458h reserved 15-9 reserved w 0000000b del3b[25:17] 8-0 audio group 2 delay data for channel 3. reference: section 4.7.9 on page 45 . w0 459h reserved 15-9 reserved w 0000000b del4b[7:0] 8-1 audio group 2 delay data for channel 4. reference: section 4.7.9 on page 45 . w0 ebit4b 0 audio group 2 delay data valid flag for channel 4. reference: section 4.7.9 on page 45 . w0 45ah reserved 15-9 reserved w 0000000b del4b[16:8] 8-0 audio group 2 delay data for channel 4. reference: section 4.7.9 on page 45 . w0 45bh reserved 15-9 reserved w 0000000b del4b[25:17] 8-0 audio group 2 delay data for channel 4. reference: section 4.7.9 on page 45 . w0 table 4-44: sd audio configuration and status registers (continued) address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 98 of 114 4.13.3.3 hd audio registers table 4-45: hd audio configuration and status registers address register name bit description r/w default 800h ctr_agr 15 selects replacement of audio control packets. 0: do not replace audio control packets. 1: replace all audio control packets. reference: section 4.7.11 on page 48 . r/w 0 agr 14 selects audio group replacement operating mode. reference: section 4.7.11 on page 48 . r/w 0 one_agr 13 specifies the replacement of just the group 1 audio. 0: do not replace only group 1. 1: replace only group 1. reference: section 4.7.11 on page 48 . r/w 0 ctrb_on 12 specifies the embedding of group b audio control packets. reference: section 4.7.9 on page 45 . r/w 1 asxb 11 group 2 asynchronous mode. reference: section 4.7.9 on page 45. r/w 0 afnb_auto 10 group 2 audio frame number generation. reference: section 4.7.9 on page 45 . r/w 1 ctra_on 9 specifies the embedding of group 1 audio control packets. reference: section 4.7.9 on page 45 . r/w 1 asxa 8 group 1 asynchronous mode. reference: section 4.7.9 on page 45 . r/w 0 afna_auto 7 enables group 1 audio frame number generation. reference: section 4.7.9 on page 45 . r/w 1 afn_ofs[2:0] 6-4 offset to add to generated audio frame number. must be in the range of 0 to 4. the resulting audio frame number will wrap around so as to always be in the 1-5 range. reference: section 4.7.16 on page 51 . r/w 000b idb[1:0] 3-2 specifies the group 2 audio to embed. note: should ida and idb be set to the same value, they automatically revert to their default values. reference: section 4.7.10 on page 47 . r/w 01b (normal mode) 11b (cascade mode) ida[1:0] 1-0 specifies the group 1 audio to embed. note: should ida and idb be set to the same value, they automatically revert to their default values. reference: section 4.7.10 on page 47 . r/w 00b (normal mode) 10b (cascade mode) 801h reserved 15-0 reserved. w n/a
gs1582 data sheet 40117 - 1 november 2007 99 of 114 802h reserved 15 reserved r 0 aes_errd 14 stereo pair d audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 aes_errc 13 stereo pair c audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 aes_errb 12 stereo pair b audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 aes_erra 11 stereo pair a audio input parity error when using aes format. automatically cleared when read. reference: section 4.7.17.1 on page 53 . r0 acpg4_det 10 set while group 4 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 acpg3_det 9 set while group 3 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 acpg2_det 8 set while group 2 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 acpg1_det 7 set while group 1 audio control packets are detected. reference: section 4.7.2 on page 37 . r0 adpg4_det 6 set while group 4 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 adpg3_det 5 set while group 3 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 adpg2_det 4 set while group 2 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 adpg1_det 3 set while group 1 audio data packets are detected. reference: section 4.7.2 on page 37 . r0 acs_apply_waitb 2 set while the gs1582 is waiting for a status boundary in the group b group before applying the acsr[183:0] data to that group. reference: section 4.7.18 on page 55 . r0 acs_apply / acs_apply_waita 1 set while the gs1582 is waiting for a status boundary in group a before applying the acsr[183:0] data. reference: section 4.7.18 on page 55 . r/w 0 acs_regen 0 specifies that audi o channel status of all channels should be replaced with acsr[183:0] field. 0: do not replace channel status 1: replace channel status of all channels reference: section 4.7.18 on page 55 . r/w 0 table 4-45: hd audio configuration and status registers address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 100 of 114 803h reserved 15-10 reserved. r n/a en_cascade 9 cascade. r/w reserved 8-0 reserved. r n/a 804h-807h reserved 15-0 reserved. r n/a 808h amd[1:0] 15-14 audio input format selector for stereo pair d channels 7 and 8. reference: section 4.7.17 on page 52 . r/w 11b amc[1:0] 13-12 audio input format selector for stereo pair c channels 5 and 6. reference: section 4.7.17 on page 52 . r/w 11b amb[1:0] 11-10 audio input format selector for stereo pair b channels 3 and 4. reference: section 4.7.17 on page 52 . r/w 11b ama[1:0] 9-8 audio input format selector for stereo pair a channels 1 and 2. reference: section 4.7.17 on page 52 . r/w 11b mute8 7 audio input channel 8 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute7 6 audio input channel 7 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute6 5 audio input channel 6 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute5 4 audio input channel 5 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute4 3 audio input channel 4 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute3 2 audio input channel 3 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute2 1 audio input channel 2 mute enable. reference: section 4.7.23 on page 62 . r/w 0 mute1 0 audio input channel 1 mute enable. reference: section 4.7.23 on page 62 . r/w 0 table 4-45: hd audio configuration and status registers address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 101 of 114 809h reserved 15, 12 reserved r/w 0 gp1_wclk_src[1:0] 14-13 audio group 1 word clock source selector. reference: section 4.7.20 on page 57 . r/w 0 gp1_ch4_src[2:0] 11-9 audio group 1 channel 4 source selector. reference: section 4.7.19 on page 56 . r/w 011b gp1_ch3_src[2:0] 8-6 audio group 1 channel 3 source selector. reference: section 4.7.19 on page 56 . r/w 010b gp1_ch2_src[2:0] 5-3 audio group 1 channel 2 source selector. reference: section 4.7.19 on page 56 . r/w 001b gp1_ch1_src[2:0] 2-0 audio group 1 channel 1 source selector. reference: section 4.7.19 on page 56 . r/w 000b 80ah reserved 15, 12 reserved r/w 0 gp2_wclk_src[1:0] 14-13 audio group 2 word clock source selector. reference: section 4.7.20 on page 57 . r/w 10 gp2_ch4_src[2:0] 11-9 audio group 2 channel 4 source selector. reference: section 4.7.19 on page 56 . r/w 111b gp2_ch3_src[2:0] 8-6 audio group 2 channel 3 source selector. reference: section 4.7.19 on page 56 . r/w 110b gp2_ch2_src[2:0] 5-3 audio group 2 channel 2 source selector. reference: section 4.7.19 on page 56 . r/w 101b gp2_ch1_src[2:0] 2-0 audio group 2 channel 1 source selector. reference: section 4.7.19 on page 56 . r/w 100b table 4-45: hd audio configuration and status registers address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 102 of 114 80bh en_not_locked 15 asserts audio_int when locked is not asserted. reference: section 4.7.14 on page 50 . r/w 0 en_no_video 14 asserts audio_int when the video format is unknown. reference: section 4.7.14 on page 50 . r/w 0 en_mux_errb 13 asserts audio_int when the mux_errb flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_mux_erra 12 asserts audio_int when the mux_erra flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_errd 11 asserts audio_int when the aes_errd flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_errc 10 asserts audio_int when the aes_errc flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_errb 9 asserts audio_int when the aes_errb flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_aes_erra 8 asserts audio_int when the aes_erra flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg4_det 7 asserts audio_int when the acpg4_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg3_det 6 asserts audio_int when the acpg3_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg2_det 5 asserts audio_int when the acpg2_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_acpg1_det 4 asserts audio_int when the acpg1_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg4_det 3 asserts audio_int when the adpg4_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg3_det 2 asserts audio_int when the adpg3_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg2_det 1 asserts audio_int when the adpg2_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 en_adpg1_det 0 asserts audio_int when the adpg1_det flag is set. reference: section 4.7.14 on page 50 . r/w 0 table 4-45: hd audio configuration and status registers address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 103 of 114 80ch mux_errb 15 set in cascade mode when the incoming video contains packets with the same group number as group 2. reference: section 4.7.3 on page 38 . r0 mux_erra 14 set in cascade mode when the incoming video contains packets with the same group number as group 1. reference: section 4.7.3 on page 38 . r0 xpoint_error 13 set when the crosspoint switch is configured to put the same audio channel in both group 1 and group 2. reference: section 4.7.19 on page 56 . r0 mute_all 12 mutes all input audio channels. reference: section 4.7.23 on page 62 . r/w 0 lsb_firstd 11 causes the fourth stereo pair serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 lsb_firstc 10 causes the third stereo pair serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 lsb_firstb 9 causes the second stereo pair serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 lsb_firsta 8 causes the first stereo pair serial input formats to use lsb first. reference: section 4.7.17 on page 52 . r/w 0 act8 7 specifies embedding of audio group 2 channel 4. reference: section 4.7.12 on page 50 . r/w 1 act7 6 specifies embedding of audio group 2 channel 3. reference: section 4.7.12 on page 50 . r/w 1 act6 5 specifies embedding of audio group 2 channel 2. reference: section 4.7.12 on page 50 . r/w 1 act5 4 specifies embedding of audio group 2 channel 1. reference: section 4.7.12 on page 50 . r/w 1 act4 3 specifies embedding of audio group 1 channel 4. reference: section 4.7.12 on page 50 . r/w 1 act3 2 specifies embedding of audio group 1 channel 3. reference: section 4.7.12 on page 50 . r/w 1 act2 1 specifies embedding of audio group 1 channel 2. reference: section 4.7.12 on page 50 . r/w 1 act1 0 specifies embedding of audio group 1 channel 1. reference: section 4.7.12 on page 50 . r/w 1 table 4-45: hd audio configuration and status registers address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 104 of 114 80dh reserved 15-0 reserved. w n/a 820h-836h reserved 15-8 reserved. w n/a 820h acsr[7:0] 7-0 audio status block byte 0. reference: section 4.7.18 on page 55 . w 85h 821h acsr[15:8] 7-0 audio status block byte 1. reference: section 4.7.18 on page 55 . w 08h 822h acsr[23:16] 7-0 audio status block byte 2. reference: section 4.7.18 on page 55 . w2ch 823h-836h acsr[183:24] 7-0 remaining audio status. reference: section 4.7.18 on page 55 . w0 840h reserved 15-9 reserved w 0000000b del1_2a[7:0] 8-1 audio group 1 delay data for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 ebit1_2a 0 audio group 1 delay data valid flag for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 841h reserved 15-9 reserved w 0000000b del1_2a[16:8] 8-0 audio group 1 delay data for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 842h reserved 15-9 reserved w 0000000b del1_2a[25:17] 8-0 audio group 1 delay data for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 843h reserved 15-9 reserved w 0000000b del3_4a[7:0] 8-1 audio group 1 delay data for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 ebit3_4a 0 audio group 1 delay data valid flag for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 844h reserved 15-9 reserved w 0000000b del3_4a[16:8] 8-0 audio group a delay data for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 845h reserved 15-9 reserved w 0000000b del3_4a[25:17] 8-0 audio group 1 delay data for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 table 4-45: hd audio configuration and status registers address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 105 of 114 4.14 jtag test operation when the jtag/host input pin of the gs1582 is se t high, the host interface port will be configured for jtag te st operation. in this mode, pins j9, j10, k9, and k10 become tdo, tck, tms, and tdi. in addition, the reset_trst pin will operate as the test reset pin. boundary scan testing using the jtag interface will be enabl ed in this mode. there are two ways in which jtag can be used on the gs1582: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of a host processor for applications such as system power on self tests. 846h reserved 15-9 reserved w 0000000b del1_2b[7:0] 8-1 audio group 2 delay data for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 ebit1_2b 0 audio group 2 delay data valid flag for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 847h reserved 15-9 reserved w 0000000b del1_2b[16:8] 8-0 audio group 2 delay data for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 848h reserved 15-9 reserved w 0000000b del1_2b[25:17] 8-0 audio group 2 delay data for channels 1 and 2. reference: section 4.7.9 on page 45 . w0 849h reserved 15-9 reserved w 0000000b del3_4b[7:0] 8-1 audio group 2 delay data for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 ebit3_4b 0 audio group 2 delay data valid flag for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 84ah reserved 15-9 reserved w 0000000b del3_4b[16:8] 8-0 audio group 2 delay data for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 84bh reserved 15-9 reserved w 0000000b del3_4b[25:17] 8-0 audio group 2 delay data for channels 3 and 4. reference: section 4.7.9 on page 45 . w0 table 4-45: hd audio configuration and status registers address register name bit description r/w default
gs1582 data sheet 40117 - 1 november 2007 106 of 114 when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the te sts are to be applied only at ate, this can be accomplished with tri-state bu ffers used in conjunction with the jtag/host input signal. this is shown in figure 4-31 . figure 4-31: in-circuit jtag alternatively, if the test ca pabilities are to be used in the system, the host processor may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the inte rface at ate. this is represented in figure 4-32 . figure 4-32: system jtag note: scan coverage is limited to digital pi ns only. there is no scan coverage for analog pins vco, sdo/sdo , rset, lf, and cp_res. note: the sd/hd pin must be held low during scan and therefore has no scan coverage. please contact your gennum representat ive to obtain the bsdl model for the gs1582. application host gs1582 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe application host gs1582 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe tri-state
gs1582 data sheet 40117 - 1 november 2007 107 of 114 4.15 device reset in order to initialize all internal operating conditions to their default states, hold the reset_trst signal low for a minimum of t reset = 10ms after all power supplies are stable. there are no requirements for power supply sequencing. when held in reset, all device outputs will be driven to a high-impedance state. figure 4-33: reset pulse supply voltage reset_trst t reset 95% of nominal level nominal level reset reset t reset
gs1582 data sheet 40117 - 1 november 2007 108 of 114 5. application reference design 5.1 typical application circuit (part a) audio interrupt standby timing_select audio channels 7 & 8 audio channels 5 & 6 jtag/host pclk input (f rom gs4911b) locked gnd_a bnc control signals gnd_a bnc blank primary group audio clock primary audio group enable ioproc_en/dis 20bit/10bit fvh input[2:0] (f rom gs4911b) sdo_en/dis audio channels 1 & 2 audio signals audio channels 3 & 4 secondary group word clock ain7_8 a_int en_grp1 wclk_2 aclk_1 en_grp2 ain3_4 ain1_2 ain5_6 aclk_2 wclk_1 primary group word clock dvb_asi standby resetn sdo_en/disn blankn jtag/hostn smpte_by passn detect_trs 20bit/10bitn ioproc_en/disn timing_sel detect_trs +3.3v_cd sd/hd sd/hdn dvb-asi 10n +3.3v 1u +1.8v_a 0r 1u 0r 10n 10n +1.8v data_in14 10n gspi[3:0] 10kr gnd_a data_in15 a_int 75r 5n6 75r 5n6 sdin sclk 4u7 4u7 +3.3v 22k r and l form the output return loss compensation network. subject to change h/hsync_gs 4911b data_in16 en_grp1 75r 10n 75r data_in17 aclk_1 io_vdd +1.8v pclk_1582 1 2 1u 1 2 1u 10n 10n 0r smpte_by pass +3.3v 0r data_in18 np np wclk_1 data_in19 resetn ain1_2 10n vco_vcc ain3_4 c* en_grp2 sdo_en/disn dvb_asi standby sd/hdn vco_gnd aclk_2 3r3 wclk_2 ain5_6 data_in0 r* ain7_8 data_in1 sdout secondary audio group enable vco_gnd data_in2 data_in3 csn reset cp_res b7 vco_vcc a8 vco_gnd b8 core_gnd e7 vco a9 tim_861 g3 pclk b4 io_vdd g1 din18 a2 din19 b3 lf a7 cp_vdd a10 cp_gnd b10 din17 a1 core_vdd k8 grp1_en/dis h6 detect_trs f3 core_gnd e6 vco_gnd b9 din16 b2 core_vdd g10 pd_vdd a6 pd_vdd b6 core_gnd d5 standby d3 aclk_1 k7 wclk_1 j7 ain_1/2 j6 din14 c2 din15 b1 core_gnd c5 core_gnd b5 nc d6 nc d7 dvb_asi g5 locked h4 grp2_en/dis h5 ain_3/4 k6 din12 c3 din13 c1 nc d8 nc e8 nc f8 sd/hd e3 core_gnd e5 core_vdd e1 aclk_2 k5 io_vdd h10 din10 d2 din11 d1 rsv f4 core_gnd j8 core_gnd g9 20bit/10bit g4 core_gnd f5 core_vdd a5 wclk_2 j5 io_gnd g2 din8 f2 din9 f1 core_gnd f7 cd_gnd f9 cd_gnd e9 ioproc_en/dis g7 smpte_by pass g6 reset g8 ain_5/6 j4 blank h3 din6 h2 din7 h1 cd_gnd d9 core_gnd e2 audio_int h7 cs_tms k9 sclk_tck j10 sdout_tdo j9 ain_7/8 k4 h/hsync a4 din4 j2 din5 j1 core_gnd f6 pd_gnd c8 pd_gnd c7 pd_gnd c6 sdo_en/dis d4 sdin_tdi k10 v/vsy nc c4 io_gnd h9 din2 k2 din3 k1 rset f10 cd_vdd e10 sdo c10 sdo d10 cd_gnd c9 jtag/host h8 f/de a3 nc e4 din0 k3 din1 j3 gs1582 place as close as possible to the pins of the gs1582. connect directly to pins of gs1582. data_in4 analog power filtering gnd_a data_in5 +1.8v_a gnd_a smpte_by passn data_in6 parallel data input[19:0] data_in7 gnd_a jtag/hostn +3.3v_cd anc_blankn ioproc_en/disn gnd_a 20bit/10bitn data_in8 detect_trs gnd_a ti mi n g_sel data_in9 data_in10 vco_gnd vco_gnd vco_gnd data_in11 vco_gnd vco_gnd vco_vcc vco_gnd 2.5v internal isolated power vctr 5 gnd 4 gnd 8 gnd 2 vcc 7 o/p 1 nc 3 gnd 6 go1555 10n 1 2 33uf +3.3v_cd 750r +/- 1% data_in12 v/vsy nc_gs4911b f/de_gs4911b +3.3v_cd 1u secondary group audio clock 1u data_in13 0r 10n (aclk and wclk may be supplied by gs4911b audio clock outputs.) *r & c: refer to section 4.11.2 for loop filter component values.
gs1582 data sheet 40117 - 1 november 2007 109 of 114 5.2 typical application circuit (part b) (to gs1582 and audio sy nchronization dev ices.) gs4911b a udio clocks[2:0] vdd_io_a io_vdd video standard select[5:0] 1v8_pclk_a gnd_bridge/phs_a gnd_vpll/all_a +1.8v +3.3v 10k vdd_core_a h_in vdd_core_a v_in aclk_gs4911b wclk_gs4911b mclk_gs4911b f_in 1v8_pclk_a gnd_vpll/all_a gnd_xtal_a f/de_gs 4911b h/hsync_gs4911b v/vsy nc_gs4911b 22r 22r 22r gnd_xtal_a +1.8v +1.8v vdd_xtal_a 0r 0r vid_std2 vid_std3 vdd_io_a vid_std4 vid_std5 (np) (np) 22r 22r 22r vdd_io_a gnd_bridge/phs_a gnd_bridge/phs_a gnd_xtal_a gnd_vpll/apll_a jtag/hostn vdd_io_a ref_lost_a 1v8_bridge/phs_a 1v8_pclk_a 1v8_pclk_a gnd_vpll/apll_a vdd_core_a gnd_vpll/apll_a 1v8_bridge/phs_a gnd_bridge/phs_a vdd_io_a 1v8_bridge/phs_a gnd_bridge/phs_a vdd_core_a vdd_xtal_a 1v8_pclk_a vdd_io_a vdd_io_a lock_lost_a genlockn vid_std1 vid_std0 vid_pll_gnd 4 vid_pll_vdd 3 xtal_vdd 5 x1 6 x2 7 xtal_gnd 8 core_gnd 9 phs_gnd 55 phs_vdd 54 analog_vdd 10 nc 11 analog_gnd 12 aud_pll_gnd 13 aud_pll_vdd 14 10fid 15 hsync 16 vsync 17 io_vdd 18 fsync 19 nc 20 vid_std0 21 vid_std1 22 vid_std2 23 vid_std3 24 vid_std4 25 vid_std5 27 aclk1 28 aclk2 29 aclk3 30 io_vdd 31 core_vdd 26 asr_sel2 32 asr_sel1 33 asr_sel0 34 timing_out1 35 timing_out2 36 io_vdd 38 timing_out4 39 timing_out3 37 timing_out5 40 lvds/pclk3_vdd 45 pclk3 46 lvds/pclk3_gnd 48 pclk3 47 pclk2 49 pclk1&2_gnd 52 pclk1 51 io_vdd 50 timing_out6 41 timing_out7 42 timing_out8 43 pclk1&2_vdd 53 lock_lost 1 ref_lost 2 genlock 64 core_vdd 44 jtag/host 56 sclk_tclk 57 sdin_tdi 58 sdout_tdo 59 cs_tms 60 reset 61 io_vdd 62 nc 63 gnd_pad 65 gs4911b 1m 27.000mhz 24pf 38pf vdd_xtal_a resetn vdd_xtal_a gnd_vpll/apll_a 1v8_pclk_a gnd_xtal_a 1v8_bridge/phs_a +3.3v decoupling @ pins 18,31,38,50,62 100nf 100nf 10uf 0r 0r 100nf 100nf decoupling @ pin 45 10uf 10uf 10nf 10nf 0r 10nf 100nf 10uf 0r 10uf 100nf 10uf 0r 10nf vdd_core_a 10nf 10nf 0r 100nf 10uf 10nf 100nf 10nf 10uf decoupling @ pin 54 decoupling @ pin 5 gnd_bridge/phs_a 1v8_bridge/phs_a 10uf control signals jtag/host 100nf 0r 10uf genlockn resetn 100nf jtag/hostn reset genlock control 10nf 10nf decoupling @ pins 26,44 1v8_bridge/phs_a 0r sdin_gs4911b csn_gs4911b sclk_gs4911b sdout_gs4911b gspi_gs4911b[3:0] fvh timing input[2:0] pclk output (to gs1582) analog power filtering fvh output[2:0] (to gs1582)
gs1582 data sheet 40117 - 1 november 2007 110 of 114 6. references & relevant standards smpte 125m component video signal 4:2:2 ? bit parallel interface smpte 259m 10-bit 4:2:2 component and 4fsc com posite digital signals - serial digital interface smpte 260m 1125 / 60 high definition producti on system ? digital representation and bit parallel interface smpte 267m bit parallel digital interface ? co mponent video signal 4:2:2 16 x 9 aspect ratio smpte 272m formatting aes/ebu audio and auxiliary data into digital video ancillary space smpte 274m 1920 x 1080 scanning analog and parallel digi tal interfaces for multiple picture rates smpte 291m ancillary data pa cket and space formatting smpte 292m bit-serial digital interface for high-definition television systems smpte 293m 720 x 483 active line at 59.94 hz progressive scan production ? digital representation smpte 296m 1280 x 720 scanning, analog and digita l representation and analog interface smpte 299m 24-bit digital audio format for hdtv bit-serial interface smpte 352m video payload identification for digital television interfaces smpte rp165 error detection checkwords and st atus flags for use in bit-serial digital interfaces for television smpte rp168 definition of vertical interval sw itching point for synchronous video switching
gs1582 data sheet 40117 - 1 november 2007 111 of 114 7. package & ordering information 7.1 package dimensions
gs1582 data sheet 40117 - 1 november 2007 112 of 114 7.2 marking diagram 7.3 packaging data 7.4 ordering information pin 1 id gs1582 xxxxe3 yyww yyww - date code yy - 2-digit year ww - 2-digit week number xxxx - l ot/work order id parameter value package type 11mm x 11mm 100-ball lbga package drawing reference jedec m0192 (with exceptions noted in package dimensions on page 111 ). moisture sensitivity level 3 junction to case thermal resistance, j-c 15.4c/w junction to air thermal resistance, j-a (at zero airflow) 37.1c/w junction to board thermal resistance, j-b 26.4c/w psi, 0.4c/w pb-free and rohs compliant yes part number package pb-free temperature range GS1582-IBE3 100-ball bga yes -20c to 85c
gs1582 data sheet 40117 - 1 november 2007 113 of 114 8. revision history version ecr pcn date changes and/or modifications a 141222 ? march 2007 new document. b 144894 ? april 2007 changed pin f4 to rsv and added drive strength values for pin h4, h7, and j9 in pin assignment and pin descriptions . modified input voltage range parameter in absolute maximum ratings . updated serial output intrinsic jitter value in ac electrical characteristics . added digital input/output circuits in section 3. added note to section 4.7.20 audio word clock . 0 145472 ? june 2007 converted to preliminary data sheet. changes were made in the following areas; table 1-1: pin descriptions , 2.1 absolute maximum ratings , 2.2 recommended operating conditions , 2.3 dc electrical characteristics , 2.4 ac electrical characteristics , 4.3 smpte mode , 4.3.1 hvf timing , 4.6 standby mode , 4.7.20 audio word clock , 4.8 ancillary data insertion , 4.8.3 vanc insertion , 4.9.4.1 smpte 352m payload identifier packet insertion , 4.9.4.3 edh generation and insertion , 4.11.2 loop filter , 4.11.3 lock detect output , 4.13.1 command word description , table 4-44: sd audio configuration and status registers , table 4-45: hd audio configuration and status registers , 4.15 device reset , 5.1 typical application circuit (part a) , 7.1 package dimensions , 7.2 marking diagram , 7.3 packaging data , 7.4 ordering information , 1 146167 ? november 2007 converted to a data sheet. updates to: note 4 in table 2-2 on page 18 , audio modes of operation on page 38 , arbitrary, smpte 352m & edh packet detect on page 40 , table 4-3 on page 39 , ancillary data insertion , separate line mode on page 63 , concatenated mode on page 64 , command word description on page 78 , gspi host interface , table 4-33 , video standard indication , 2.3 dc electrical characteristics , ancillary data checksum generation and insertion , table 2-3: ac electrical characteristics , interrupt control , smpte 352m payload identifier packet insertion , sd formats and hd formats .
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2006 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs1582 data sheet 40117 - 1 november 2007 114 of 114 document identification data sheet the product is in production. gen num reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible.

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